[1] [1] WANG D, ZHU X G, GUO X, et al. A 26 GS/s 8-bit time-interleaved SAR ADC in 55 nm CMOS technology ［J］. Elec, 2019, 8(3): 305-316.

[3] [3] GINSBURG B P, ChANDRAKASAN A P. 500-MS/s 5-bit ADC in 65-nm CMOS with split capacitor array DAC ［J］. IEEE J Sol Sta Circ, 2007, 42(4): 739-747.

[4] [4] ZHU Y, CHAN C H, CHIO U F, et al. A 10-bit 100-MS/s reference-free SAR ADC in 90 nm CMOS ［J］. IEEE J Sol Sta Circ, 2010, 45(6): 1111-1121.

[5] [5] LIU C C, CHANG S J, HUANG G Y, et al. A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure ［J］. IEEE J Sol Sta Circ, 2010, 45(4): 731-740.

[6] [6] ZHU Z M, XIAO Y, SONG X L. VCM-based monotonic capacitor switching scheme for SAR ADC ［J］. Elec Lett, 2013, 49(5): 327-328.

[7] [7] RAHIMI E, YAVARI M. Energy-efficient high-accuracy switching method for SAR ADCs ［J］. Elec Lett, 2014, 50(7): 499-501.

[8] [8] LI J W, GUO X, JIAN L, et al. A 1 GS/s 12-bit pipelined/SAR hybrid ADC in 40 nm CMOS technology ［J］. Elec, 2020, 9(2): 375-393.

[9] [9] ZHONG J Y, ZHU Y, SIN S W, et al. Multi-merged- switched redundant capacitive DACs for 2b/cycle SAR ADC ［C］ // IEEE 54th Int MWSCAS. Seoul, South Korea. 2011: 1-4.

[10] [10] CHAN C H, ZHU Y, SIN S W, et al. A 38 mW 8 b 1 GS/s 2b/cycle interleaving SAR ADC with compact DAC structure ［C］ // Symp VLSIC. Honolulu, HI, USA. 2012: 86-87.

[11] [11] CHAN C H, ZHU Y, ZHANG W H, et al. A two-way interleaved 7-b 24-GS/s 1-then-2 b/cycle SAR ADC with background offset calibration ［J］. IEEE J Sol Sta Circ, 2018, 53(3): 850-860.

[12] [12] NAM J W, HASSANPOURGHADI M, ZHANG A Y, et al. A 12-bit 16, 32, and 64 GS/s 4-b/cycle time-interleaved SAR ADC with dual reference shifting and interpolation ［J］. IEEE J Sol Sta Circ, 2018, 53(6): 1765-1779.