The dynamic polarization controller (DPC) is a crucial component in fiber optic communication^[1–3], optical imaging^[4], and quantum technologies^[5–12]. It can transform any input state of polarization (SOP) into any desired SOP to overcome polarization-related impairments, which result from high internally and externally induced birefringence. With the rapid developments in optical communication technology and large-scale optical integration technology, it is imperative to realize the traditional functions of optical polarization processing on an integration platform. In the quantum communication field, a number of research works for integrating the quantum key distribution (QKD) system on silicon photonics integrated circuits have been reported. However, a fiber DPC or manual polarization controller (MPC) was usually used instead of an on chip DPC. It is desired that the DPC can be integrated into the overall QKD chip^[13–17].

Several promising platforms on integrated optic polarization controllers have been reported^[18–21]. The architectures of the first two works are not based on the silicon-on-insulator (SOI) platform, which is compatible with the complementary metal-oxide-semiconductor fabrication technology that is more compact and economical. The design in Ref. [20] has several functions; however, arbitrary polarization-based coordinate conversion cannot be performed because no symmetrical 2D grating is used to couple the light out from the chip. The design in Ref. [21] cannot realize the endless polarization control. Especially, the DPC based on the simulated annealing method was not explored, and the results of the dynamic extinction ratio were not investigated.

In this work, we design and demonstrate a full silicon photonics integrated DPC. By employing the variable step simulated annealing approach, we achieve a dynamic polarization extinction ratio greater than 25 dB. The experimental results agree well with theoretical simulation. The performance of the compact silicon photonics integrated polarization controller is close to that of the commercial fiber DPC. The overall size of the DPC on chip was 2.830mm×0.210mm×1mm, which was much smaller than that of fiber-squeezers-based DPC.

In Section 2, the design of the silicon photonics integrated DPC is presented. In Section 3, the characters of the thermal phase shifters (TPSs) are evaluated. There is good linearity between the phase shift and the power consumed by the metal heater. The modulation bandwidth is about 30 kHz. In Section 4, we present the numerical simulation and experimental results of the silicon photonics integrated DPC. The advantages of the variable step simulated annealing approach are demonstrated, and a dynamic polarization extinction ratio larger than 25 dB is obtained. Finally, Section 5 presents the ways to improve the performance of the DPC and the conclusions.

Generally, the DPC comprising three or four fiber squeezers was utilized in fiber communication systems. The fiber squeezers were activated by piezoceramic actuators, which were driven by the high voltage of above 100 V. The squeezers alternated between 0°, 45°, 0°, and 45° of orientation. Each squeezer introduced a phase shift between the linear polarization components aligned parallel and perpendicular to the squeezing direction. The phase shift can be varied by altering the squeezing force. The fiber under the stress can be represented in Jones calculus by two kinds of transformation matrices M0 and M45, as indicated in Eq. (1): M0=(e−iδ0/200eiδ0/2),M45=(cos(δ45/2)−isin(δ45/2)−isin(δ45/2)cos(δ45/2)),(1)where δ0 and δ45 are the delayed phases due to stressed fiber birefringence. The matrix M45 can be transformed to a product of matrix M0 and matrices, which describe 50/50 couplers, as follows: $$\begin{gathered} M45=(cos(δ45/2)−isin(δ45/2)−isin(δ45/2)cos(δ45/2)) \\ =(1/2−1/21/21/2)(e−iδ45/200eiδ45/2)(1/21/2−1/21/2). \end{gathered}$$(2)

The transformation matrices can be transformed into the corresponding structures of silicon photonics integrated circuits, as demonstrated in Fig. 1^[22]. The blue lines denote the waveguides. The red and black rounded rectangles denote the TPSs and 50/50 multimode interferometers (MMIs), respectively.

According to the above basic structures, the DPC consisting of silicon photonics integrated circuits was designed, as indicated in Fig. 2(a). The input and output ports were 2D grating couplers (GCs) that were utilized as the polarization beam splitter (PBS)^[23]. The structure was symmetrical, the input port can be utilized as an output port, and vice versa. Four 1×2 50/50 MMI couplers were inserted into the waveguides for the purpose of testing and aligning, where one output port of each 1×2 MMI coupler is connected to a one-dimensional (1D) GC or a photodiode. The 1550 nm laser beam in single-mode (SM) fiber with an arbitrary SOP can be guided into the integrated DPC by a vertical coupling approach. Each linear polarization component is directed into one waveguide with TE mode using the 2D GC. Following a series of transformations, such as M1(M0), M2(M45), M3(M0), and M4(M45), the two TE modes of each waveguide are coupled out to another SM fiber through the 2D GC.

Figure 2(b) indicates the photograph of silicon photonics integrated DPC. The fabrication of the device was performed with CSiP180Al active flow technology. It was based on a 200 mm SOI substrate with 2 µm buried oxide (BOX) and 220 nm top silicon. The overall size of the DPC was 2.830mm×0.210mm×1mm, which was much smaller than that of the fiber-squeezers-based DPC with the size of 83mm×20.32mm×16mm (PolaRITE III, GP). Here, TPS was employed to alter the delayed phase. The 25 µm golden wire was selected to bond the pad by which the driving voltage can be applied on the DPC. The characters of the TPS are evaluated in detail in the next section.

The characters of the TPS or TiN metal heater are evaluated utilizing a Mach–Zehnder (MZ) modulator. The length of the TPS is 400 µm, and the resistance of the metal heater is 1.97 kΩ. A 1 mW 1550 nm continuous laser beam was coupled into one port of the 2×2 MZ modulator. By varying the voltage on the metal heater of one side, the output power was altered. We transformed the voltage into the power applied on the metal heater utilizing the expression P=V2/R,(3)where R denotes the resistance of the metal heater.

As shown in Fig. 3(a), there is a good linearity between the phase shift and the power consumed by the metal heater. The total phase shift is roughly 3π by varying the power from 0 to 50.56 mW, which corresponds to the applied voltage from 0 to 10 V. The phase shift amount is enough to stabilize the polarization with the simulated annealing method. Note that many digital-to-analog converter chips’ output voltages can reach this voltage, and a high voltage amplifier is unnecessary. In contrast, the voltage of 140 V is required to drive the piezo of PolaRITE III.

In addition, the modulation speed of the phase was evaluated, which determines the polarization locking speed. In the measurement, a 40 µs electronic square pulse with a peak voltage of 5.6 V was applied to the metal heater of the MZ modulator. It corresponds to a phase shift of π. The rising time was measured to be 11 µs, and the falling time is 5.9 µs. This value is about one-tenth of the rise time of PolaRITE III. Thus, the modulation bandwidth is about 30 kHz.

The simulated annealing approach is a good approach to lock the output SOP. Usually, a big step is needed to realize high-speed polarization controlling. However, from the simulation, we discovered that to obtain a higher polarization extinction ratio, a small step is necessary. To address this issue, the variable step approach was adopted to increase the speed and extinction ratio of the SOP locking simultaneously. The flow chart of the program is illustrated in Fig. 4.

We started by setting the initial temperature as T0=1K. The variable m is used to count the external loops, and the number of the total loops is m0=10 in a round. The variable n is used to count the internal loops, and the number of the total loops is n0=50 in an external loop. There are totally 500 internal loops in a round. The maximal intensity of the input beam Iin is normalized. Then, we set the initial value of the four delay phases to 2π and stored them into an array Sp(θ1,θ2,θ3,θ4). Then, we calculated the output intensity Ipx according to the delay phases and the SOP of the input beam. Here, Ipx denotes the intensity of the beam from one output port of the PBS followings the DPC. Imax and Smax denote the maximum intensity of Ipx and corresponding delayed phases, respectively. Ipy denotes the intensity of the beam from the other output port of the PBS.

Before entering the external loop, the value m was initialized to one, and the value T1 was initialized to T0. In the external loop, the temperature decreases with the proportion function: Tn+1=pTn,(4)where the value of p is set to 0.2. It determines the temperature changing speed. When entering the internal loop, we employed the random variable step function RV(Ipx,Iin) to generate random phase delay Sr. The random variable step function is expressed as follows: Sr={Sp+st·r,Sp+c·st·r,Sp−st·r,Sp≤00<Sp<3π3π≤Sp,(5)where r denotes the random numbers between 0 and 1, c denotes the random numbers of −1 or 1, and st represents the search step. Usually, when the step st is larger, the search loops are less. However, the disturbance generated by the large step st is also higher, making a high extinction ratio of SOP difficult to obtain. We proposed to use a variable step st to improve the extinction ratio and, at the same time, to maintain a high search speed. The variable steps are indicated by st={0.16rad,0.08rad,0.03rad,0.008rad,0.1<Ist≤10.01<Ist≤0.10.001<Ist≤0.01Ist≤0.001,(6)where Ist=1−Ipx defines the gap between the normalized maximum intensity 1 and Ipx.

The simulation results are shown in Fig. 5. The fixed step method with two different steps and the variable step method were compared. When the step was larger (st=0.16rad), the required internal loops were less. However, the extinction ratio is lower. For a smaller step of st=0.008rad, a higher extinction ratio can be obtained at the cost of more internal loops to reach the steady value. It is obvious that the best result is achieved by the variable step simulated annealing methods, where the highest extinction ratio is obtained with the least internal loops.

Note that the static polarization extinction ratio, electronic noises of the photodetectors, and fluctuations of the optical power determine the ultimate limit of the DPC. In the simulation, the minimum intensity of Ipy is set to Ipx·10−2.8, considering the statistic polarization extinction ratio of the 2D GC of 28 dB. The standard variance of the electronic noises and optical power fluctuation is set to 5×10−4 (normalized to the maximum intensity of one).

The scheme of the test setup is illustrated in Fig. 6. A 1550 nm fiber pigtailed DFB laser was utilized to generate a continuous beam, and a variable optical attenuator is used to tune the intensity of the laser beam. Part of the beam, which was employed to monitor the laser power, was separated by a 50/50 fiber SM coupler. An MPC is employed to tune the SOP of the beam directed into the chip. An alignment machine was utilized to align the fiber to the top of the 2D GC nearly vertically with an angle of 80°. The power coupled into the chip is 1 mW. The measured total loss from the input 2D GC to the output 2D GC is ∼20dB. The coupling loss of the fabricated 2D GC is 7 dB. Considering the 3 dB loss from the 50/50 MMI on the chip, the transmission loss of the integrated DPC is 3 dB, which mainly originates from the four MMIs. After transmitting through the chip, the beam was directed into the SM fiber again. Then, it was separated by the fiber PBS into path 1 and path 2. The intensity of the beam in the paths was evaluated by detector 1 and detector 2. The DPC on the chip is exploited to maximize the intensity of the beam in path 1 (detector 1), and, therefore, the intensity of the beam in path 2 (detector 2) is minimized.

Based on the simulation results, we employed the variable step approach to lock the SOP of the laser. The output voltage limit of the multifunction input/output (I/O) card was 10 V. From Section 3, this voltage range can result in a phase shift of 3π. This phase shift range is enough to lock the SOP by setting the initial phase shift at 2π. By fitting the experiment results in Fig. 3(a), a linear formula can be obtained as follows: θ=c·P+θbias,(7)where c=164.85rad/mW, and θbias=0.93rad. Combined with Eq. (3), the relationship between the voltage step ΔV and corresponding phase step Δθ can be written as ΔV=R2cVΔθ.(8)

From Eq. (8), we observe that ΔV decreases with the voltage V for a constant Δθ. When the value of voltage V is small, the voltage step ΔV will be very large. The minimum value ΔVmin corresponds to the maximum value of Vmax, and it is not relevant to θbias. In our experiment, ΔVmin was used to ensure more stable polarization control for the corresponding Δθ or st value.

The experiment results of our silicon photonics integrated dynamic polarization controlling are shown in Fig. 7. Before the operation of the DPC control procedure, the voltage of detector 2 was set to the maximum value by the MPC. For the measurement range of detector 2, its output was saturated at the beginning of the DPC control. The black line represents the results utilizing a fixed step of 0.005 V (0.008 rad at V=10V) with ∼600 internal loops. The red line represents the results utilizing a fixed step of 0.1 V (0.16 rad at V=10V) with ∼100 internal loops. The blue line represents the results utilizing a variable step. For the variable step approach, a extinction ratio higher than 25 dB is obtained with ∼100 internal loops. This value is nearly close to the static extinction ratio of 28 dB of our silicon photonics integrated DPC. The experimental results are similar to the simulation results in Fig. 5. To achieve a better dynamic polarization extinction ratio in experiment, a low noise photodetector should be utilized, and multiple samples were averaged to minimize the electronic noise and optical power fluctuation.

For further study, it is very promising to decrease the coupling efficiency of the silicon photonics integrated DPC from 7 dB to 2 dB or less by using the butting coupling method with an appropriate spot size converter between the on-chip silicon waveguide and SM fiber. On the SM fiber side, a fiber lens or large numerical aperture optical fiber is recommended. On the integrated DPC side, the spot size converter and polarization rotator-splitter should be used to replace the 2D GC^[24]. In consideration of deleting the unnecessary 1×2 MMI coupler, the total insertion loss can be reduced to about 6.8 dB. In the situations of less reset, the structure of the DPC can be simplified from 0°, 45°, 0°, 45° to 0°, 45°, 0°. Then, the total insertion loss will be reduced to about 5.4 dB.

The modulation bandwidth of the DPC designed by us is about 30 kHz. Considering the voltage of 5.6 V applied on the TPS, the bandwidth-voltage product is 5.6×30=168kHz·V. Therefore, the bandwidth-voltage product is much higher than the commercial product based on squeezing the fiber (PolaRITE III with driving board PCD - M02), which has a typical value of 1.25 kHz·V. More importantly, the high voltage about 140 V is no longer needed. Considering that a faster modulation speed is needed in some cases, the P-I-N phase shifter based on the plasma dispersion effect of silicon can be used to replace the TPS. The modulation bandwidth of tens of MHz or higher can be achieved. However, the insertion loss of the P-I-N phase shifter is higher, and the loss increases with the phase shift amount. This will affect the balance of the two arms and decrease the polarization extinction ratio of the DPC. Typically, for a 500 µm long P-I-N phase shifter, the insertion loss is about 0.5–1 dB or even smaller. The excess insertion loss is 0.1–0.2 dB when the phase shift amount is π, and the excess insertion loss is 0.5–1 dB when the phase shift amount is 3π.

Compared with the polarization controllers based on silicon photonics integrated circuits^[20,21], our DPC utilizes an output 2D GC and 0°/45°/0°/45° structure, which makes it able to realize arbitrary polarization-based coordinate conversion with endless polarization control.

In conclusion, we have designed and demonstrated a compact silicon photonics integrated DPC. The structures and principles of operation were presented in detail. A polarization extinction ratio higher than 25 dB was achieved with the variable step simulated annealing approach. Numerical simulation was used to optimize the experimental parameters. The methods to decrease the loss and increase the modulation speed for the device are also discussed. With the butting coupling method and polarization rotator-splitter, the effective transmission loss will be significantly reduced, resulting in a better transmission performance of fiber communication systems. It is expected that the device can also find applications in silicon photonics integrated QKD systems.