Fig. 1. (a) TX equalization, (b) RX equalization, (c) proposed package-level equalization.

Fig. 2. Circuit model for the high-frequency package network of a DML. The S parameters of the package assembly are measured using the vector network analyzer, and the s2p file is embedded in the circuit. The inset shows the bond wire between the chip pad and the package assembly.

Fig. 3. Contour maps of gain strength versus inductance and capacitance at frequencies of 10, 15, 20, 25, 30, and 35 GHz.

Fig. 4. Measured (symbol lines) and simulated (solid lines) transmission parameters of the bond wire used in the DML module. The inset shows the designed measure fixture and the equivalent circuit model used to extract the bonding-induced capacitance.

Fig. 5. Contour map of gain strength versus inductance and capacitance at 22 GHz. The labels show the corresponding gain strengths under the two bond wire length conditions.

Fig. 6. Frequency responses of the DML module packaged with and without equalization conditions, measured at a laser current of 90 mA.

Fig. 7. Experimental setup for single-wavelength PAM4 signal transmission.

Fig. 8. BER versus the modulation speed with and without equalization cases.

Fig. 9. BER of 112 Gbps PAM4 signal versus the ROP for the BtB case.