Fig. 1. Schematic diagrams of integrated DFB on TFLN by flip-chip bonding. (a) Schematic diagram of 3D structure and cross-section of flip-chip bonding, SSC and height-limiting structure are important to overall performance; (b) schematic diagram of SSC, the SSC includes a SiN waveguide directly connected to the TFLN ridge waveguide with tilted angle, and part 1 and part 2 are aimed to obtain the best mode overlap field with DFB

Fig. 2. Design and optimization of interface part (part 1) between SSC and TFLN waveguide. (a) Structure parameters and mode field of TFLN ridge waveguide, insert image shows SEM result after dry etching; (b) diagram of joint part between SiN and TFLN waveguide and corresponding parameters; (c) mode overlap between SiN structures (for different H₁,H₂,and W₁) and TFLN ridge waveguide; (d) mode field and structural parameters of SiN waveguide in optimal design; (e) influence of L₁ on conversion efficiency; (f) electric field distribution at different positions when L₁=10 μm

Fig. 3. Design and optimization of interface part between SSC and DFB. (a) Target mode field distribution of DFB; (b) schematic diagram of part 2 in SSC; (c) influence of SiON thickness on SSC single-mode condition; (d) mode coincidence degree between SSC and target DFB for different W₂, W₃, and G; (e) structural parameters and mode field of optimal coincidence degree

Fig. 4. Conversion efficiency of part 2. (a) Influence of L₂ on SSC efficiency η₂; (b) corresponding electric field of part 2 when L₂=100 μm under optimal parameters

Fig. 5. Conversion efficiency of SSC for different wavelengths

Fig. 6. Conversion efficiency between different size mode field and proposed scheme. (a) Mode field and electric field distribution of the designed structure at different positions corresponding to coupling with single-mode fiber with diameter of 10 μm; (b) mode field and corresponding electric field distribution of the designed structure at different positions for coupling with small mode field DFB chip with diameter of 3 μm

Fig. 7. Processing diagram of integrated DFB on TFLN by flip-chip

Fig. 8. Influence of different processing error on conversion efficiency. (a) Conversion efficiency corresponding to different TFLN inclination angle; (b) horizontal position deviation between SiON thin layer and central waveguide; (c) thin layer thickness; (d) fabrication error of top layer SiN tip on SSC