Fig. 1. Architecture of infrared image processing SOC chip system

Fig. 2. Structure of image preprocessing module

Fig. 3. Flow chart of nonuniformity correction algorithm

Fig. 4. Structure of image enhancement module

Fig. 5. Verification of stripe elimination (a) Original image with stripe noise (b) Verification of line offset correction of regional mean (c) Verification of frequency domain 2D median filtering (d) Verification of adaptive filtering of LMS

Fig. 6. Verification of scene-based nonuniformity correction (a) original diagram before correction (b) Verification of neural network method (c) Verification of high pass filter correction

Fig. 7. Verification of image enhancement (a) Original diagram (b)Verification of Retinex algorithm (c)Verification of global histogram equalization (d)Verification of transform domain enhancement -logarithmic transform

Fig. 8. Infrared image processing SoC chip (a)SoC chip layout(b)SoC die

Fig. 9. Infrared imaging device (a) 1 280×1 024 uncooled infrared imaging device，(b) 1 024×768 uncooled infrared imaging device

Fig. 10. Miniaturized low power infrared detection microsystem movement, principle prototype and imaging (a) 1 024×768 imaging movement. (b) 1 280×1 024 infrared detection system principle prototype, (c) Imaging of 1 024×768, (d) Imaging of 1 280×1 024

Fig. 11. Nonuniformity correction test effect of 1 280×1 024 imaging microsystem principle prototype (a) no NUC in readout circuit, no NUC in SoC chip. (b) NUC in readout circuit chip, no NUC in SoC chip (c) NUC in readout circuit chip + NUC in SoC chip

Fig. 12. Diagram of target detection and target tracking of 1 280×1 024 imaging microsystem principle prototype