Fig. 1. Circuit schematic diagram of self-triggered pulse adder

Fig. 2. Pulse adder auxiliary circuit design

Fig. 3. Self-triggering drive conduction circuit and self-triggering discharge circuit

Fig. 4. Truncated loop for self-trigger drive

Fig. 5. Simulated waveforms of nine-stage gate voltage

Fig. 6. Output waveform with 10 kΩ load

Fig. 7. Waveforms of the fifth-stage driving voltage

Fig. 8. Image of the proposed self-triggering pulse adder

Fig. 9. 1 kHz repetitive voltage waveform

Fig. 10. Output voltage waveforms of adder

Fig. 11. Output voltage waveform at different loads

Fig. 12. Output waveform of different voltage amplitudes under a resistor-capacitance series load