[1] J Montanaro, R T Witek, K Anne et al. A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor. IEEE J Solid-State Circuits, 31, 1703(1996).

[2] P Nuzzo, F de Bernardinis, P Terreni et al. Noise analysis of regenerative comparators for reconfigurable ADC architectures. IEEE Trans Circuits Syst I, 55, 1441(2008).

[3] L X Shen, N Sun, Y Shen et al. A two-step ADC with a continuous-time SAR-based first stage. IEEE J Solid-State Circuits, 54, 3375(2019).

[4]

[5]

[6] B Razavi, B A Wooley. Design techniques for high-speed, high-resolution comparators. IEEE J Solid-State Circuits, 27, 1916(1992).

[7] M H White, D R Lampe, F C Blaha et al. Characterization of surface channel CCD image arrays at low light levels. IEEE J Solid-State Circuits, 9, 1(1974).

[8]

[9] S Yoshihara, Y Nitta, M Kikuchi et al. A 1/1.8-inch 6.4 MPixel 60 frames/s CMOS image sensor with seamless mode change. IEEE J Solid-State Circuits, 41, 2998(2006).

[10] R Kapusta, H Y Zhu, C Lyden. Sampling circuits that break the kT/C thermal noise limit. IEEE J Solid-State Circuits, 49, 1694(2014).

[11]

[12] J A Fredenburg, M P Flynn. A 90-MS/s 11-MHz-bandwidth 62-dB SNDR noise-shaping SAR ADC. IEEE J Solid-State Circuits, 47, 2898(2012).

[13]

[14]

[15]

[16]

[17] S L Li, B Qiao, M Gandara et al. A 13-ENOB second-order noise-shaping SAR ADC realizing optimized NTF zeros using the error-feedback structure. IEEE J Solid-State Circuits, 53, 3484(2018).

[18] L Jie, B Y Zheng, M P Flynn. A calibration-free time-interleaved fourth-order noise-shaping SAR ADC. IEEE J Solid-State Circuits, 54, 3386(2019).

[19]

[20]

[21]

[22] H Y Zhuang, W J Guo, J X Liu et al. A second-order noise-shaping SAR ADC with passive integrator and tri-level voting. IEEE J Solid-State Circuits, 54, 1636(2019).

[23] J X Liu, S L Li, W J Guo et al. A 0.029-mm² 17-fJ/conversion-step third-order CT ΔΣ ADC with a single OTA and second-order noise-shaping SAR quantizer. IEEE J Solid-State Circuits, 54, 428(2019).

[24]

[25]

[26]

[27] J X Liu, C K Hsu, X Y Tang et al. Error-feedback mismatch error shaping for high-resolution data converters. IEEE Trans Circuits Syst I, 66, 1342(2019).

[28] J Liu, G Wen, N Sun. Second-order DAC MES for SAR ADCs. Electron Lett, 53, 1570(2017).