Fig. 1. (Color online) (a) Left, 24 WUJI chips on a 4-inch sapphire wafer. Right, a close-up optical image of a 6 mm × 6 mm die with 5900 MoS₂ transistors and peripheral I/O pads. (b) Scaled schematic of the RV32-WUJI die’s physical layout, with the bottom layer being MoS₂ on sapphire. (c) Transfer curves of the inverter’s 50 load and 50 drive transistors. (d) Static voltage transfer traits of 900 inverters with noise tolerance. (e) Gain value distribution of 50 inverters. SS is subthreshold swing; VTG is top-gate voltage. (f) The 17-stage longest logic gate path has a 171 μs max delay. (g) Upper left shows circuit structures like controlled full adders, 4-input multiplexers, counters, and a 32-bit register. Upper right shows their basic logic functions. (h) Data path schematic through the nine modules^[11].