Fig. 1. Schematic diagram of narrow pulse generation circuit based on a transistor

Fig. 2. Response simulation results of various points in the circuit

Fig. 3. Flow chart of narrow pulse generation

Fig. 4. Real picture of a transistor-based narrow pulse generation circuit

Fig. 5. Measured results of pulse wareforms under different conditions

Fig. 6. Forward/reverse bias block diagram and equivalent circuit of the SRD

Fig. 7. Schematic diagram of SRD combined with a delay line to generate narrow pulse circuit

Fig. 8. Schematic diagram of the narrow pulse formation process

Fig. 9. Simulation results of a narrow pulse’s output signal

Fig. 10. Block diagram of narrow pulse generation

Fig. 11. Physical diagram of SRD pulse generation circuit

Fig. 12. Transmission lines with different lengths

Fig. 13. Measured results at different frequencies and different transmission line lengths

Fig. 14. Effect of transmission line length on pulse width and amplitude

Fig. 15. Pulse waveform of 7 V_pp at 50 MHz (L_d=5 cm)

Fig. 16. Optical pulse measurement