Microelectronics, Volume. 52, Issue 2, 301(2022)

A 12 bit 1.6 GS/s Folding and Interpolating A/D Converter Based on 0.13 μm SiGe BiCMOS Process

ZOU Peizhe1,2, WANG Yonglu2,3, and YI Zhou1
Author Affiliations
  • 1[in Chinese]
  • 2[in Chinese]
  • 3[in Chinese]
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    References(5)

    [4] [4] DAI Z Y, CAO F B, YE F, et al. Digital encoding module used in a 6-bit 133-GS/s folding and interpolating ADC [C]// 13th IEEE ICSICT Proceed. Hangzhou, China. 2016: 1601-1603.

    [5] [5] WANG L F, MENG Q, HE WW, et al. Digital encoding calibrated unit used in 8 bit 1 GS/s folding and interpolating ADC [J]. Elec Lett, 2016, 52(5): 83-87.

    [8] [8] MIKHEEV R, MALYGIN A. Formalization of folding and interpolating ADC architecture [C]// IEEE EIConRus. Moscow, Russia. 2018: 1401-1403.

    [10] [10] QU R Y, ZONG S N, DANG H. Non-ideality analysis of folding and interpolating ADC [C]// 4th ICCET. Singapore. 2012: 31-35.

    [11] [11] D’AMICO S, COCCIOLO G, SPAGNOLO A, et al. A 765-mW 5-bit 90-nm 1-Gs/s folded interpolated ADC without calibration [J]. IEEE Trans Instrum & Measur, 2015, 63(2): 295-303.

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    ZOU Peizhe, WANG Yonglu, YI Zhou. A 12 bit 1.6 GS/s Folding and Interpolating A/D Converter Based on 0.13 μm SiGe BiCMOS Process[J]. Microelectronics, 2022, 52(2): 301

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    Paper Information

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    Received: Jun. 28, 2021

    Accepted: --

    Published Online: Jan. 16, 2023

    The Author Email:

    DOI:10.13911/j.cnki.1004-3365.210240

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