1Institute of Semiconductor Science and Technology, South China Normal University, Foshan 528225, China
2College of Electrical Engineering, Hebei University of Architecture, Zhangjiakou 075000, China
3State Key Laboratory of Optoelectronic Materials and Technologies, School of Physics, Sun Yat-sen University, Guangzhou 510275, China
4Henan Key Laboratory of Diamond Optoelectronic Materials and Devices, Key Laboratory of Materials Physics, Ministry of Education, School of Physics and Laboratory of Zhongyuan Light, Zhengzhou University, Zhengzhou 450052, China
5Department of Physics, The University of Hong Kong, Hong Kong 999077, China
Realization of positive and negative optical responses in a single device promises construction of multifunctional optoelectronic devices. This work demonstrates a mixed-dimensional heterojunction junction field-effect transistor (JFET) with positive and negative photoresponse regulatory functions by gate voltage. The device achieves a remarkable negative responsivity exceeding 425 mA/W. Additionally, benefiting from Fowler-Nordheim tunneling (FNT) behavior, the mixed-dimensional JFET exhibited an excellent negative response performance with response and decay times of 50.1 ms and 53.9 ms and a high ratio of 343 at and under 635 nm illumination. Additionally, the JFET’s negative photoresponse is sensitive to both gate voltage and light intensity, which can be used to realize NAND logic gate and optical communication functions. These results unveil the promising potential of mixed-dimensional optoelectronic devices for optical communication, and logic device technologies.
【AIGC One Sentence Reading】:Ga2O3/WSe2 mixed-dimensional JFET shows gate-tunable positive/negative photoresponses, enabling NAND logic and optical communication, highlighting potential for multifunctional optoelectronic devices.
【AIGC Short Abstract】:A Ga2O3/WSe2 mixed-dimensional heterojunction JFET demonstrates gate-tunable positive and negative photoresponses. The device shows high negative responsivity and fast response/decay times, making it suitable for optical communication and logic gate applications. This work highlights the potential of mixed-dimensional optoelectronic devices.
Note: This section is automatically generated by AI . The website and platform operators shall not be liable for any commercial or legal consequences arising from your use of AI generated content on this website. Please be aware of this.
1. INTRODUCTION
Driven by advancements in artificial intelligence driving, there is need for developing new technologies in mobile communications, new energy vehicles, robotics and drones, as well as miniaturized and multi-functional chips with high performance. Consequently, it is essential to develop optoelectronic devices that integrate multifunctional components. Traditional photodetectors have typically utilized single photoresponses to achieve high efficiency, responsivity, and fast response rate [1–4]. However, there has been limited research on incorporating both positive and negative photoresponses into a single photodetector. Combining positive and negative responses into a single photodetector would increase the versatility of the device for multiple applications, such as artificial vision adaption mimicking [5,6], multimode optoelectronic logic gates [7], and visual signal reception and preprocessing [5]. Among these emerging applications, the optoelectronic logic gate is a new type of logic application to achieve faster and larger capacity data transmission and processing [3,4,7–9].
Compared to the two-terminal devices, junction field-effect transistors (JFETs) provide advantages such as faster response, lower sensitivity to electrostatic discharge, and adjustable photoresponse modulated by gate voltage. These features make JFETs highly suitable for optoelectronic logic gate devices. [10–13]. Two-dimensional transition metal dichalcogenides (2D TMDs) exhibit strong light-matter interactions, free of surface dangling bonds and high carrier mobility, as compared to traditional semiconductors [14–17]. 2D TMD heterojunctions have many advantages like broadband optical absorption, efficient interlayer carrier transport, simple fabrication process, and potential of fabricating flexible devices [18]. Recent research has explored combining 2D materials with gallium oxide () to fabricate junction field-effect transistors, including [19,20], [21], [21], [22–24], [20], [25,26], [27], and [28,29]. These devices exhibit excellent performance due to outstanding air stability, electrical characteristics, and transparency of .
One-dimensional (1D) microwires (MWs) with high crystallinity can serve as the active optical material to enhance light management and charge collection for developing novel optoelectronic devices [30,31]. For instance, Lu et al. constructed a photodetector array based on 1D Sn-doped MWs for solar-blind imaging [32]. Lately, the same group simplified the readout circuits of the solar-blind photodetector array by weaving the Sn-doped microbelts into the lattice structures, which exhibited excellent performance with a low dark current and rapid response time [33]. To date, 1D -based transistors have demonstrated excellent performance in terms of low noise current, rapid response, specific detectivity, and high external quantum efficiency [32,33].
In this work, a novel 1D/2D mixed-dimensional heterojunction transistor and a JFET are presented, with a 2D nanosheet serving as both the gate dielectric layer and the photosensitive layer. Under optical illumination with a wavelength of 635 nm, the device exhibits both positive and negative photoresponses, which are modulated by the gate voltage. Notably, the negative photoresponse performs better than the positive response. We further elucidate the effects of gate voltage and laser intensity on the JFET’s negative photoresponse. Specifically, the mixed-dimensional heterojunction JFET demonstrates an outstanding transistor performance, including a high ratio up to 343, response time of 50.1 ms, and decay time of 53.9 ms at and . The transport mechanism of the hetero-structure is also studied. Notably, at the high gate bias (), the carrier transport is dominated by Fowler-Nordheim tunneling (FNT) behavior. Furthermore, using the gate voltage and optical illumination as the two inputs, the function of the NAND logic gate is realized on the JFET. Subsequently, the output signal can be realized as the binary conversion by the computer. Overall, the mixed-dimensional JFET provides a paradigm for -based transistors to implement logical operations, dual-band detection, and optical communication.
2. EXPERIMENTAL SECTION
A. Growth of Microwires
A 50 nm Au film was deposited onto the silicon substrate by thermal evaporation. The high-purity (99.999%) powder and C (99.95%) powder in a ratio of 3:1 were mixed in a mortar. The mixed powder and the Au-film-coated Si substrates were placed in the quartz tube, and the Si substrates were placed 15 cm downstream from the high-temperature zone. The quartz tube was first flushed with ultrapure argon (99.999%) for 6 min, and then the tube furnace was heated at a rate of up to 1100°C and maintained at this temperature for 60 min under a constant nitrogen flow of 150 sccm. The white flocculent product obtained at the end of the growth process consisted of the microwires.
B. Device Construction
A small quantity of microwires were dispersed in the ethanol solution and then transferred to a substrate using a rubber-tipped burette. The sample was annealed at 150°C for 30 s to eliminate the residual effects of the ethanol solution. nanosheets were exfoliated from single crystals using a mechanical stripping method and then transferred onto a PVA/PDMS film. With the three-dimensional positional adjusting platform, the nanosheet was aligned and transferred to the microwires, thus forming the p-n heterojunctions. The device was spin-coated, prebaked, and fabricated using an ultraviolet maskless lithography machine [TuoTuo Technology (Suzhou) Co., Ltd.]. Subsequently, the source, drain, and gate electrode (10 nm Cr/50 nm Au) were deposited using an electron beam evaporation instrument to form a Schottky contact.
C. Materials and Device Characterization
The morphology of the samples was characterized using scanning electron microscopy (SEM), while elemental analysis of the materials was conducted by the energy dispersive X-ray spectroscopy (EDS). The thickness of the and was determined by the atomic force microscopy (AFM). X-ray diffraction (XRD) was employed to investigate the crystal structure. The micro-Raman spectrometer was used for characterizing the . The electrical and optoelectronic properties of the JFET were measured at room temperature using the Keithley 2636B semiconductor device analyzer. All measurements were performed under ambient conditions at room temperature.
3. RESULTS AND DISCUSSION
High-crystal MWs were synthesized by chemical vapor deposition (CVD) to construct the mixed-dimensional heterojunction JFETs [34]. Figure 1(a) shows the SEM image of the as-fabricated microwires. A single microwire with a smooth surface features a spherical particle at its tip. To understand the growth mechanism of microwires, was subsequently extracted for EDS characterization. In Fig. 1(b), EDS mapping images of MW-tipped nanoparticles fabricated at 1100°C are presented [35]. Here, the MWs have distinct gold particles at their tips [36]. The growth of MWs follows the vapor-liquid-solid mechanism, consistent with existing literature [34–36]. Additionally, the structures and phase purity of the as-grown nanostructures were characterized by XRD. Comparing with the standard PDF card (PDF# 41-1103) of material, the observed diffraction peaks were consistent with the standard peaks of material [as shown in Fig. 1(c)]. The room temperature Raman spectra of the deposited nanostructures are shown in Fig. 1(d), revealing the 12 Raman active modes at low frequency (below ), medium frequency () [37], and high frequency (above ). The low-frequency modes such as 112.3, 142.6, 167.7, and are attributed to the translational and low-frequency vibrations between the tetrahedral chains and the octahedral chains, while the 318.0, 345.7, 414.2, and signals are attributed to the octahedral chains. The high-frequency modes such as 628.3, 653.3, 656.9, and are associated with the stretching and bending of the tetrahedral chains. The XRD and Raman results confirm the single pure phase of the MWs.
Figure 1.(a) SEM image of microwires. (b) EDS mapping image of Au. (c) XRD patterns of microwires grown at 1100°C. (d) Raman spectrum of microwires.
Figures 2(a) and 2(b) show the schematic and the optical microscope image of the mixed-dimensional heterojunction JFET, respectively. To fabricate the JFET, mechanically stripped was dry-transferred onto a 1D MW and deposited with 10 nm Cr/50 nm Au electrodes to form a Schottky contact. The EDS mapping image shows that the JFET consists of Ga, O, W, and Se elements [as shown in Fig. 2(c)], and the elemental distribution is consistent with the spatial distribution of the heterotransistor materials [38]. To determine the thicknesses of each layer in the mixed-dimensional heterojunction JFET, the AFM images were obtained and the thicknesses of the and flake were 688 nm and 44 nm [as shown in Figs. 2(d) and 2(e), respectively]. To further analyze the energy band structure between the and , kelvin probe force microscopy (KPFM) is employed to reveal the Fermi level shift of and [as shown in Fig. 2(f)]. Figure 2(g) shows the difference of the surface potential difference (SPD) of the measured interface [as denoted by the red line in Fig. 2(f)]. Before contact, the Fermi level of the is lower compared to that of the as shown in Fig. 2(h). Upon contact, the Fermi energy level difference between and drives electrons flowing from to , forming a thin depletion region at the heterojunction interface [19], and creating an accumulation of electrons in and holes in as shown in Fig. 2(i).
Figure 2.(a) Schematic illustration of the JFET. (b) Optical microscopy image of the JFET. (c) EDS mapping images of the Ga, O, W, and Se elements. AFM measurement of the thickness of (d) and (e) . (f) KPFM image at the interface. (g) SPD plot of the measured interface. Energy band of the heterojunction (h) before and (i) after contact.
To further analyze the electrical performance of the JFET, measurements of the JFET were conducted in the dark, with results as shown in Fig. 3(a). The JFET demonstrated effective rectification behavior in the absence of illumination. To understand the optoelectronic response, the device was further investigated under 635 nm illumination. Figure 3(b) shows the time-dependent photocurrent of the JFET with the gate bias of and . The device shows a positive photoresponse when and a negative photoresponse when . Moreover, both the negative and positive photocurrent responses increase with increasing optical power [as shown in Figs. 3(c) and 3(d)].
Figure 3.(a) curves at under dark conditions. (b) Temporal response of the device for 635 nm illumination at and 5 V. (c), (d) Time-dependent photocurrent of the JFET under light illumination at 635 nm at and () in response to different laser power. (e) Time-dependent photoresponse under 100 on/off switching cycles. (f) A single modulation cycle at and under 635 nm illumination for estimating both the rise and fall times.
Comparing to the positive photoresponse, the negative photoresponse shows more excellent performance. Under 635 nm illumination, the JFET demonstrated a remarkably high negative photoresponse achievable with , having the ratio of 343. To study the stability of the negative photoresponse, a 100 switching cycle test was performed. The current magnitude of the device remained nearly constant, indicating the high reliability and stability of the JFET [as shown in Fig. 3(e)]. Response time and decay time are important parameters for evaluating the phototransistor. The measured 10%–90% response time and decay time are 50.1 ms and 53.9 ms, respectively. The device gives a fast response speed under gate voltage and light illumination [as shown in Fig. 3(f)].
To investigate the influence of gate voltage and light intensity on the negative photoresponse of the JFET, output curves of different gate voltages and laser powers were measured. Under 635 nm illumination with a power density of , the maintains a low resistance. Meanwhile, increasing the gate voltage widens the depletion region of the . This depletion reduces the current flow in the channel, necessitating a larger bias voltage to provide carriers. Consequently, a rightward shift is observed in the output curve [Fig. 4(a)]. Figure 4(d) shows the output curves of the JFET at a constant of 5 V under different laser powers. As the laser power increases, the resistance of decreases and the depletion region in the widens at . Consequently, the output curves exhibit a rightward shift.
Figure 4.(a) Output curves at different gate voltages of the JFET under 635 nm illumination with a power intensity of . (b) Photocurrent and detectivity as a function of different gate voltages at . (c) Responsivity and external quantum efficiency of JFET under different gate voltages. (d) Output curves at of the JFET under different laser powers. (e) Photocurrent and detectivity as a function of different laser powers at . (f) Responsivity and external quantum efficiency of JFET under different laser powers at .
It is well known that responsivity (), external quantum efficiency (EQE), and specific detectivity () are important indexes for evaluating phototransistors. To further evaluate the optoelectronic performance of JFET, the responsivity, detectivity, and external quantum efficiency of the JFETs with different gate voltages and laser powers were quantitatively measured. The parameters of , and EQE are calculated according to the following equations [39–41]:
In the given formulas, is the current in the dark condition, and represents the current in the light condition. denotes the net photocurrent under light. It is calculated as the difference between the current under light condition () and the dark current () of the device. and represent the light power density and the effective area of the device, respectively. The Planck’s constant () is , the light speed () is , and the element charge () is . denotes the excitation wavelength, which is specified to be 635 nm. The , and EQE are calculated using the four provided formulas under various conditions.
As shown in the Fig. 4(b), net photocurrent significantly increases under 635 nm illumination while the gate voltage increases from 0 V to 5 V, indicating that the gate voltage has a regulatory effect on the channel. Figure 4(c) demonstrates the relationship between the gate voltage and the EQE and . With the increase of the gate voltage, the depletion region becomes widened at the heterojunction interface. The and EQE of the device gradually increase under the combined effect of light illumination and gate voltage, and the can reach 425 mA/W and the EQE reaches 83.18%. This enhanced modulation by the gate voltage is likely the cause of these results. As shown in Figs. 4(e) and 4(f), the net photocurrent gradually increases with the enhancement of optical power while . However, the , , and EQE decrease, which may be caused by carrier lifetime shortening due to Auger recombination [42,43].
The curves of the JFET under dark and light conditions at are shown in Fig. 5(a). Under dark conditions, remains constant (33–34 nA) with varying . Under 635 nm illumination, there is a positive net photocurrent for ranging from to , and a negative photocurrent for ranging from to 5 V. In contrast, under dark conditions, the high resistance of hinders the modulation of the channel current by . However, light illumination generates a number of electron-hole pairs in , thereby reducing its resistance and creating a conductive path for to modulate the channel conductance. Varying the gate voltage affects the width of the depletion region, thereby influencing the electrical and optical characteristics of the device. Figure 5(b) shows the curves of the JFET under dark and light conditions at . When , the magnitude of the current is equal to 0 A. The changes in the depletion region width, as discussed here, explain the variations of the photoresponse characteristics of the JFET at different conditions, as shown in Figs. 5(c)–5(f).
Figure 5.(a) curves under dark conditions and 635 nm illumination. (b) curves under dark conditions and 635 nm illumination. (c)–(f) Energy band diagrams at the heterojunction with 635 nm illumination at different . (g) Schematic illustration of the depletion region at and (h) . (i) Fowler-Nordheim plots of current of the heterojunction device.
Owing to the difference in Fermi energy levels between and , the electrons move from to , thus creating the accumulation of electrons in and holes in . A thin depletion region forms [19] at the heterojunction interface, and the direction of the built-in electric field points from to . Therefore, increasing the gate voltage widens the depletion region, as visually depicted in Figs. 5(c)–5(f). When [Fig. 5(c)], the photoelectrons in flow into the channel. This narrows the depletion region in , leading to an increased current compared to that in the dark condition [as shown in Fig. 5(g)]. When , the magnitude of the current is the same as in the dark condition [Fig. 5(d)]. This indicates that the Fermi levels of and are aligned, and the width of the depletion region remains the same as in the dark condition. With , the magnitude of the current is equal to 0 A because the electrons are not energetic enough to cross the barrier [Fig. 5(e)]. With the increase of gate voltage, the electrons flow into ; when , the depletion region in widens significantly, pinching off the channel, resulting in the low as shown in Fig. 5(h).
In order to further explore the physical mechanism of the device, the Simons approximation is used to model the current transport of the heterojunction, and the model can be described by the following equations [9,44–46]: where is the gate voltage, is the width of the tunneling barrier, is effective mass of the carrier, and is the barrier height. Figure 5(i) shows the fitted result, which can be divided into two regions. At the low gate voltage (region II), the electrons flow from to ; thus the current of the channel is relatively low. However, as the gate voltage increases, the depletion region becomes larger and the electrons cannot cross the barrier. At large gate voltages, the barrier in the depletion region will become more triangular and thus the electrons will undergo FNT behavior, causing the gate current to increase dramatically, which in turn affects the channel current and causes the channel current to decrease.
The adjustable positive and negative photoresponses exhibited by the JFET in response to variations in gate voltage and light intensity hold potential applications in logic gate operations and communication systems. Figure 6(a) shows a schematic illustration of the JFET under 635 nm illumination. To demonstrate the potential applications of JFET, its combined optical and electrical characteristics are utilized to design a NAND logic gate, as depicted in Fig. 6(b). More concretely, the 635 nm laser serves as input 1 (represented by “ON” for a logical “1” and “OFF” for a logical “0”). Similarly, the gate voltage is defined as input 2 (represented by “” for a logical “1” and “” for a logical “0”). The current is defined as “output”, of which the high-level current and low-level current correspond to the values “1” and “0”, respectively. It can be easily found that output 1 is obtained only under the condition of input and input , as shown in Figs. 6(c) and 6(d). Additionally, when the output signals of the JFET exhibit four grounds of “01010011”, “01000011”, “01001110”, “01010101”, the computers take first the input signals to convert into “S”, “C”, “N”, “U” for American Standard Code for Information Interchange (ASCII) as shown in Fig. 6(e). Over all, these results demonstrate that the JFET has great promising prospects in the field of logic device technology and optical communication.
Figure 6.(a) Schematic diagram of the JFET under 635 nm illumination. (b) Schematic illustration of NAND logic gate. (c) Truth table corresponding to JFET. (d) Realized logic function with respect to the input of and light. (e) Schematic diagram of the binary code translation based on the JFET.
In summary, we have successfully synthesized microwires using CVD and fabricated a 1D/2D mixed-dimensional JFET. In this structure, nanosheets serve as the gate dielectric layer and light photosensitive layer. Notably, they have minimal impact on the channel currents under the dark condition. Under illumination at 635 nm, the JFET exhibits gate-tunable positive and negative photoresponses. When , a negative response was realized through FNT behavior. Our device exhibits a reliable and consistent negative photoresponse. Notably, the reached 425 mA/W at and under 635 nm illumination with a power intensity of . The response and decay times of the JFET have reached 50.1 ms and 53.9 ms, respectively. Additionally, our device achieves logic operation and optical communication by utilizing positive and negative photoresponses. This successful realization of the mixed-dimensional JFET provides a feasible approach for the realization of optical logic gates, optical communication, and photogating transistors in -based devices.