Fig. 1. Block diagram of the precision time-delay system

Fig. 2. Schematic sequence diagram of trigger jitter compensation

Fig. 3. TLV3801 Schematic diagram of the high-speed comparator design

Fig. 4. Trigger jitter measurement timing diagram

Fig. 5. TDC7200 Schematic diagram of the circuit design

Fig. 6. 30 ns time interval measurement data diagram

Fig. 7. MC100EP195 Schematic diagram of the cascade circuit design

Fig. 8. Timing diagram of data processing

Fig. 9. SiT9366 Clock circuit design schematic diagram

Fig. 10. 5 000 ps jitter test results

Fig. 11. Time-lapse rendering of 10 ps，5 120 ps and 10 240 ps