Microelectronics, Volume. 53, Issue 1, 70(2023)

A Low Power SRAM Architecture for Error-Tolerant Applications

HUANG Maohang, WANG Zilin, and HE Yajuan
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  • [in Chinese]
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    References(9)

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    [4] [4] LV J, WANG Z, HUANG M, et al. A read-disturb-free and write-ability enhanced 9T SRAM with data-aware write operation [J]. Int J Elec, 2021, 109(2): 207-217.

    [5] [5] SEEVINCK E, LIST F J, LOHSTROH J. Static-noise margin analysis of MOS SRAM cells [J]. IEEE J Sol Sta Circ, 1987, 22(5): 748-754.

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    [7] [7] PENG C P, XIAO S S, LU W J, et al. Average 7T1R nonvolatile SRAM with R/W margin enhanced for low-power application [J]. IEEE Trans VLSI Syst, 2018, 51(10): 584-588.

    [8] [8] LIN S, KIM Y B, LOMBARDI F. Design and analysis of a 32 nm PVT tolerant CMOS SRAM cell for low leakage and high stability [J]. IEEE Trans VLSI Syst, 2010, 43(2): 176-187.

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    [10] [10] HE Y, ZHANG J, WU X, et al. A half-select disturb free 11T SRAM cell with built-in write/read-assist scheme for ultra-low voltage operations [J]. IEEE Trans VLSI Syst, 2019, 27(10): 2344-2353.

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    HUANG Maohang, WANG Zilin, HE Yajuan. A Low Power SRAM Architecture for Error-Tolerant Applications[J]. Microelectronics, 2023, 53(1): 70

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    Paper Information

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    Received: Jan. 27, 2022

    Accepted: --

    Published Online: Dec. 15, 2023

    The Author Email:

    DOI:10.13911/j.cnki.1004-3365.220037

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