Fig. 1. Equipment working principle flow chart. (a) Device cross-section; (b) implementation of “OR” logic function with single transistor; (c) data is given to computer for processing; (d) schematic of PD-MOS-based binary code translation

Fig. 2. Schematic diagram of PD-MOS operating in subthreshold mode

Fig. 3. Electric field distribution

Fig. 4. Electric field strength cut at the same depth of PN junction

Fig. 5. Simulation of device current density in dark case. (a) Current density in dark case; (b) current density cut-off in horizontal direction of MOSFET channel

Fig. 6. Simulation of device current density in illumination case. (a) Current density in illumination case; (b) current density cut-off in horizontal direction of MOSFET channel

Fig. 7. I_DS-V_GS curve of PD-MOS

Fig. 8. Spectral response at gate voltage of 0.4 V

Fig. 9. Device layout, overview and package diagram. (a) Device layout; (b) device overview; (c) device package diagram

Fig. 10. Spectral response at V_GS=0.4 V

Fig. 11. Equipment used for testing. (a) Function signal generator; (b) multimeter; (c) oscilloscope; (d)(e) DC power supply; (f) test circuits

Fig. 12. Test circuit construction

Fig. 13. Comparison of light-dark current of device at V_DS=V_cathode=1 V

Fig. 14. Modulation frequency curve of device optical signal

Fig. 15. Variations of output current with light and gate voltage. (a) Variation of output current with gate voltage of 0 V with and without light; (b) variation of output current with gate voltage under dark condition

Fig. 16. Realization of "OR" logic function

Fig. 17. Schematic of binary code translation based on proposed device