With the rapid development of information technology, especially in the context of increasing requirements for data transmission and computation speed, traditional electronic logic gates face bottlenecks in terms of speed, power consumption, and integration. In contrast, optoelectronic logic gates are able to utilize the high-speed propagation characteristics of light and the parallelism that photons possess to break through these limitations and provide more efficient computation and information processing capabilities. However, current optoelectronic logic devices generally rely on heterogeneous material integration schemes or non-standard complementary metal oxide semiconductor (CMOS) processes to realize logic functions, resulting in high design and implementation costs as well as poor compatibility with standard CMOS processes. To this end, we present a photodiode-metal oxide semiconductor (PD-MOS) device prepared monolithically based on the semiconductor manufacturing international corporation (SMIC) 180 nm CMOS process platform. By independently modulating the incident light intensity and gate voltage to achieve bimodal modulation, the device can realize reconfigurable “OR” logic operations within a single silicon-based architecture. This monolithic integration strategy eliminates the need to introduce heterogeneous material stacks while maintaining full compatibility with standard CMOS manufacturing processes.

Using the Sentaurus TCAD simulation platform, the device is first modeled as a two-dimensional structure based on a standard 180 nm CMOS process, and its electrical characteristics are analyzed. The simulations focus on electric field strength under fixed bias voltage conditions, current density under illumination and in the dark, spectral responsivity, and I-V characteristics to preliminarily verify the feasibility of the device. In this paper, a fully customized layout is then designed using the Cadence Virtuoso EDA platform, and the device design and wafer processing are completed via SMIC’s 180 nm CMOS process. A test bench is built to test the I-V characteristics and spectral response curves of the device and compare them with simulation results. Finally, fixed bias voltages are provided for the drain and photodiode (PD) anode, and the gate and optical frequency are adjusted to experimentally demonstrate the “OR” logic function in a single device.

The dual-mode modulated optoelectronic device proposed in this paper benefits from high responsivity in the gate voltage-controlled depletion region, and modulation of channel conductivity. At 0.4 V gate bias, the responsivity in the wavelength range of 450?1000 nm exceeds 4×10⁴ A/W, with a peak responsivity of 1.18×10⁵ A/W at 760 nm (Fig. 10). The key mechanism is the effective separation of photogenerated carriers in the PD depletion region, which modulates the threshold voltage and increases current. The threshold voltage shifts from around 700 mV in the dark to around 400 mV under illumination (Fig. 13). Under dual modulation input conditions (optical pulse: frequency f =50 Hz, optical power P_opt=181 nW; electrical pulse: frequency f =25 Hz, amplitude V_GS=1 V), the device is capable of performing “OR” logic operations (Fig. 15, Table 1). When the device’s output signal is represented as a binary sequence, it can be decoded into corresponding characters by a computer (Fig. 17).

We present a PD-MOS device prepared monolithically based on the SMIC 180 nm CMOS process platform is presented. The device modulates its threshold voltage and, consequently, its output current via a photogenerated substrate bias effect. Experimental results show that applying a suitable positive bias to both the metal-oxide-semiconductor field effect transistor (MOSFET) drain and the PD cathode enables the photogenerated substrate bias to effectively modulate the threshold current, producing distinguishable output currents under illuminated and dark conditions, thus completing the optical modulation. Due to its unique carrier modulation mechanism, the device exhibits enhanced photoelectric conversion under standard bias (V_DS=V_cathode=1 V), with responsivity exceeding 4×10⁴ A/W across 450?1000 nm. An output current above 5×10^-7 A is defined as logic “1”, and below this threshold as “0”. Through the gate-controlled characteristics of the MOSFETs and the photogenerated carrier transport mechanism of the PD, the “OR” logic function is achieved by combining the gate-controlled operation of the MOSFET with the photogenerated carrier transport mechanism of the PD. When the output signal forms a specific binary sequence, it can be decoded into corresponding characters by a computer using the American standard code for information interchange (ASCII).