Fig. 1. Block diagram of CAP modulation communication system

Fig. 2. Linear list storage format for each order term in the Volterra algorithm. (a) Current time; (b) next time

Fig. 3. Data structure parameter update process. (a) Designed data structure; (b) data structure after executing operation ①; (c) data structure after executing operation ②; (d) data structure after executing operation ③

Fig. 4. Storage structure for the weights of each order parameter w(n). (a) Storage structure of w(n); (b) data structure after sparse operation

Fig. 5. Block diagram of DSP-based UWOC experimental system

Fig. 6. Experimental setup and site of UWOC system. (a) Transmitter; (b) water tank for the experiment; (c) receiver

Fig. 7. Experimental results of Volterra algorithm consumption. (a) On-chip consumption of different pruning conditions in Volterra algorithm with different memory lengths; (b) weights of second-order parameters after weight estimation

Fig. 8. BER of Volterra algorithm with different pruning conditions as a function of symbol rate. (a) Memory length of 10; (b) memory length of 14

Fig. 9. BER of Volterra algorithm with memory lengths of 18 and 20 under different pruning conditions as a function of symbol rate. (a) Memory length of 18; (b) memory length of 20