Fig. 1. Block diagram of the proposed 76～81 GHz quadrature transceiver

Fig. 2. （a） Schematic of the pre-amplifier with a transformer-based gm-boosted network and output power divider, （b） 3D view of the input transformer, and （c） 3D view of the output power divider.

Fig. 3. Simulated results of the gm-boosted single-stage CS amplifier

Fig. 4. （a） Inter-stage serial inductance network, （b） Inter-stage serial-parallel resonating network, and （c） The proposed LC resonating network

Fig. 5. Simulated results of the inter-stage parasitic capacitance elimination network

Fig. 6. （a） The schematic of proposed active mixer, （b） equivalent model of active mixer inter-stage impedance, and （c） noise model of active mixer and the schematic of dynamic current-bleeding.

Fig. 7. Simulated conversion gain of the active mixer using various architectures

Fig. 8. Chip photograph

Fig. 9. Measured S11 of the down-conversion mixer

Fig. 10. Measured CG of the down-conversion mixer

Fig. 11. Measured input P1dB of the down-conversion mixer

Fig. 12. Measured noise figure of the down-conversion mixer