Fig. 1. Diagram of the doubler circuit architecture.

Fig. 2. (a) Field distribution of incident frequency, and (b) field distribution of output second harmonic in the proposed doubler

Fig. 3. (a) Photograph of the fabricated D-band doubler, and (b) picture of the mounted 127 μm-thick ALN doubler circuit

Fig. 4. (a) Photograph of the D-band power-combined doubler A, (b) Photograph of the D-band power-combined doubler B

Fig. 5. Test configuration of the proposed D band doubler

Fig. 6. (a) Test results of the pumping power of D band doubler. (b) Measured results of the output power of the single D band doubler

Fig. 7. Measurement of the power-combined doubler: (a) available pumping power of the V-band amplifier, (b) output power and efficiency of combined doubler A with a bias voltage of +12V, (c) output power and efficiency of combined doubler B