[1] [1] GUO P X,HOU W G,GUO L,et al.Fault-tolerant routing mechanism in 3D optical network-on-chip based on node reuse[J].IEEE Transactions on Parallel and Distributed Systems,2020,31(3):547-564.

[2] [2] CHAUDHARI B,PATIL S.Optimized designs of low loss non-blocking optical router for ONoC applications[J].International Journal of Information Technology,2020,12(1):91-96.

[3] [3] SHI X H,WU N,GE F,et al.Srax:a low crosstalk and insertion loss 5×5 optical router for optical network-on-chip［C］//IECON 2019-45th Annual Conference of the IEEE Industrial Electronics Society,October 14-17,2019,Lisbon,Portugal.New York:IEEE,2019:3102-3105.

[4] [4] FADHEL M,GU H X and WEI W T.DORR:a DOR-based non-blocking optical router for 3D photonic network-on-chips:regular section[J].IEICE Transactions on Information and Systems,2021,104(5):688-696.

[5] [5] SU Y,XIE Y,SONG T,et al.A novel virtual-cluster based architecture of double-layer optical networks-on chip[J].Journal of Lightwave Technology,2020,38(14):3553-3562.

[6] [6] LIU F Y,ZHANG H B,CHEN Y W,et al.Wavelength-reused hierarchical optical network on chip architecture for manycore processors[J].IEEE Transactions on Sustainable Computing,2019,4(2):231-244.

[7] [7] LI M C,TSENG T M,TALA M,et al.Maximizing the communication parallelism for wavelength-routed optical networks-on-chips［C］//2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC),January 13-16,2020,Beijing,China.New York:IEEE,2020:109-114.

[8] [8] YAO R J，YE Y Y.Toward a high-performance and low-loss clos-benes-based optical network-on-chip architecture[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2020,39(12):4695-4706.

[9] [9] YANG W,CHEN Y W,HUANG Z Y,et al.Path-based routing and wavelength assignment for multiple multicasts in optical network-on-chip［C］//2019 IEEE 21st International Conference on High Performance Computing and Communications,August 10-12,2019,Zhangjiajie,China.New York:IEEE,2019:1155-1162.

[10] [10] HUANG L,Gu H X,TIAN Y H,et al.Universal method for constructing the on-chip optical router with wavelength routing technology[J].Journal of Lightwave Technology,2020,38(15):3815-3821.

[11] [11] ZHENG Z D,Li M C,TSENG T M,et al.Light:a scalable and efficient wavelength-routed optical networks-on-chip topology［C］//2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC),January 18-21,Tokyo,Japan.New York:IEEE,2021:568-573.

[12] [12] ASADINIA S,MEHRABI M,YAGHOUBI E.Surix:non-blocking and low insertion loss micro-ring resonator-based optical router for photonic network on chip[J].The Journal of Supercomputing,2021,77(1):4438-4460.

[13] [13] LEE J H,KIM M S,HAN T H.Insertion loss-aware routing analysis and optimization for a fat-tree-based optical network-on-chip[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2018,37(3):559-572.

[14] [14] WERNER S,NAVARIDS J,LUJAN M.Designing low-power,low-latency networks-on-chip by optimally combining electrical and optical links［C］//2017 IEEE International Symposium on High Performance Computer Architecture (HPCA),Febuary 4-8,2017,Austin,TX,USA.New York:IEEE,2017:265-276.

[15] [15] LU Y S,YU S J,CHANG Y W.Topological structure and physical layout codesign for wavelength-routed optical networks-on-chip［C］//2020 57th ACM/IEEE Design Automation Conference (DAC),July 20-24,2020,San Francisco,CA,USA.New York:IEEE,2020:1-6.