(1) The FinFET shows strong gate control of the channel and reaches a very high breakdown voltage. Drain-induced barrier lowering (DIBL) has been observed in β-Ga₂O₃ FinFETs, and was found to be the dominant breakdown mechanism in these devices^[22]. Fabrication complexity is one of the challenges for FinFETs, as FinFETs have to be realized by fine line lithography and are dependent on sidewall channels formed by dry etching.

(4) Annealing at oxygen environment is believed to passivate the oxygen vacancies and compensate for the surface charge from 300 °C to 1000 °C. Compensation of the surface charge not only reduces the image forces lowering but also increases the electron tunneling width, resulting in the increased Schottky barrier height and the reduced reverse leakage current^[9]. Post metallization annealing at nitrogen environment can significantly reduce the interface states, which can lead to a substantial improvement in the breakdown voltage and a significant reduction in the I–V hysteresis of the device^[10].

(3) By inserting oxidized metal layer like PtO_x or PdCoO_x in Schottky contact can lead to a higher barrier height, thereby reducing the leakage current density and improving the breakdown characteristics. However, this approach may not be conducive for the turn-on voltage^[5−7]. Combination with low work-function metal may be a preferable route for low power loss diodes^[8].

(2) The CAVET consists of the highly resistive current blocking layers (CBLs) around the conductive aperture to confine the current path. A robust CBL and a clean dielectric/semiconductor interface are needed for sustaining high reverse voltage and promoting effective/stable channel modulation respectively. Proper designs of doping schemes and aperture conductivity are also vital^[23].

(2) The absence of p-type doping in β-Ga₂O₃ poses a challenge in the development of power devices. On the one hand, we can use mesa structure or high resistivity region or PtO_x/p-NiO-based junction engineering to reduce off-state leakage. On the other hand, optimizing the thermal oxygen process/nitrogen implantation process/in situ epitaxy, studying the leakage mechanism and the formation mechanism of compensating defects will also help.

(1) The breakdown voltage and PFOM of large area devices are far inferior to the small-size devices. The high defect density and severe interface damage greatly affect device performance. To address these issues, techniques such as high aspect ratio ICP etching and BOE surface damage repair can be employed.

β-Ga₂O₃ possesses a highly promising critical electric field of 8 MV/cm, allowing devices with improved performance compared with other wide bandgap materials^{[1, 2]}. The 4-inch wafers grown from a melt and over 10 μm of the epitaxial layers grown by Halide vapor phase epitaxy (HVPE) with highly controllable doping concentration, are commercially available, paving the way of vertical power devices. The β-Ga₂O₃ community has consistently elevated the average critical electric field superior to SiC or GaN, which is suitable for medium/high voltage infrastructures demanding over 900 V^[1]. Vertical β-Ga₂O₃ power electronics have made a tremendous progress in recent years, such as various surface/interface engineering, diverse edge termination, quasi-inversion vertical transistor, etc.

(1) There are several pre-treatment methods available to ensure a reliable surface before fabricating the Schottky metal. The performance of Schottky barrier diodes (SBDs) can be significantly enhanced by employing pre-treatment methods such as piranha, Hydrochloric acid (HCl), acetone, and UV ozone. These methods can lead to improved characteristics, including near-ideal ideality factors and higher breakdown capabilities in SBDs^[3].

After a decade of development, β-Ga₂O₃ power devices have made great progress so far. However, several challenges and issues still persist.

(3) The JTE technique is a very effective technique commonly used in commercial Si and SiC devices. The p-type NiO can expand the depletion boundary to reduce the peak electric field^[16−18]. The effectiveness of NiO has been verified to improve the reverse characteristic. The mechanism behind conductivity modulation in the device, which grants it the ability to withstand surge events, remains somewhat mysterious.

Currently, there have been four kinds of vertical transistors demonstrated inβ-Ga₂O₃, including Fin field-effect transistor (FinFET), Current aperture vertical electron transistor (CAVET), Vertical diffused barrier field-effect transistor (VDBFET) and U-shaped gate trench MOSFET (U-MOSFET), as shown in Fig. 2.

(2) The high-resistance zone formed by ion implantation or oxygen annealing promotes the spreading of the potential along the surface and suppresses leakage current^[13−15]. Lattice damage and deep acceptor may affect the reliability and switching characteristics of devices.

The interface quality is the baseline to ensure the performance of device. However, with the transition of planar junction to cylindrical junction at the edge of anode, the edge electric field crowding effect becomes apparent. Thus the implementation of edge termination techniques was reached to a high level of difficulty due to the extremely high critical electric field. These techniques include the use of field plate, high-resistivity, heterojunction termination extension (JTE) and etched mesa termination, as shown in Fig. 1.

(3) The low thermal conductivity is also a big problem. Thinning the substrate combined with double-side packaging or flip-chip packaging may abate this inherent vice. Of course, these problems in the development of gallium oxide power devices still require the efforts of international community to promote the early industrialization of gallium oxide power devices.

(3) In VDBFETs or UMOSFETs, a quasi-inversion conductive channel can be formed at the surface of the CBL under a proper gate voltage^{[24, 25]}. These structures were intrinsically E-mode as the channel naturally remains non-conductive at zero gate bias because of the blocking capability of the highly resistive CBLs. CBLs realized by selective diffusion by Mg doping spin-on-glass, oxygen annealing, N implantation and N impurities during epitaxy have great impact on conduction and voltage blocking characteristics of the transistors^[26]. Oxygen annealing offers the advantage of avoiding lattice damage, unlike nitrogen implantation, and the CBL formed by oxygen annealing generating the gallium vacancies at more than 1000 °C is more stable. Additionally, oxygen annealing can form a thicker CBL depth, which is important for minimizing punch-through current and improving breakdown voltage. On the contrary, nitrogen implantation-based UMOSFET devices have more advanced performance and better controllability of CBL profile, but they come with the drawbacks of higher cost, lattice damage, and larger device leakage current. Generally speaking, UMOSFET has shown promising performance, with N implantation-based UMOSFET surpassing the unipolar theoretical limit of Si-based devices^[27]. Nevertheless, its breakdown voltage remains inferior to that of FinFET, which requires further optimization. The mechanism and controllability of the oxygen annealing process need further exploration. In addition, the device shows a nonlinear turn-on of the output current, necessitating additional investigation to understand and improve this characteristic.

In summary, the current maximum commercial wafer size is 100 mm, containing an n⁺ monocrystalline substrate and an n^- HVPE epitaxial layer. Increasing the wafer size further would lead to a reduction in the fabrication cost of gallium oxide devices. The development of interface engineering and various edge termination techniques has continually pushed the boundaries of β-Ga₂O₃ high-performance devices. U-MOSFET shows promise as potential solutions for β-Ga₂O₃ power transistors, but this structure has many uncertainties such as breakdown voltage and reverse recovery characteristics. In-depth exploration of device physics mechanisms related to interface defects and intrinsic defects is necessary. Reliable soft breakdown and ideal reverse leakage have not been achieved. Additionally, attention should be given to the development of ampere-level diodes/transistors and improving device reliability.

(4) Mesa termination provides a simple and cost-effective method, which the peak electric field can be transfered from contact edge to the mesa corner^[19−21]. Further optimizations can be made by refining the etching process to effectively control sidewall damage and interface charge.

“The interface is the device” was coined by Nobel laureate Herbert Kroemer. This famous phrase is also applicable to β-Ga₂O₃ diodes. Several surface/interface engineering methods have been applied including pre-treatment, surface etching, oxidized metal and annealing.

(1) The silicon dioxide is commonly used as dielectric for other semiconductors. However, the permittivity of silicon dioxide is relatively low compared to that of β-Ga₂O₃, making silicon dioxide less prone to experiencing breakdown before β-Ga₂O₃^[11]. Researchers have chosen high-k dielectric as the gallium oxide field plate and obtained good performance^[12].

(2) During the device preparation process, the surface of gallium oxide probably adsorbs part of the gas molecule from the surrounding environment. The performance and uniformity of devices can be significantly improved by employing dry etching techniques and minimizing the time exposed to ambient air during the preparation process^[4]. However, the insight of excellent β-Ga₂O₃ surface needs to be more investigated such as surface energy, surface absorption, dangling bonds, chemical ratios, and so on. On the other hand, it is crucial to establish a universal and simple surface treatment method that can make sure every β-Ga₂O₃ team reaches the first-rate baseline device in the near future.