Fig. 1. Architecture of digital readout circuits with column-level ADC

Fig. 2. ADC static performance DNL, INL and missing code

Fig. 3. Distribution of output codes at V_in=1.039 V

Fig. 4. Schematic block diagram of the testing system

Fig. 5. Front panel of Labview( parameter setting module)

Fig. 6. Front panel of Labview (data acquisition module and display module)

Fig. 7. DNL and INL curves

Fig. 8. Time domain diagram of digital outputs

Fig. 9. Frequency domain diagram of digital outputs