Fig. 1. Schematic and equivalent model of switching circuit

Fig. 2. Circuit topology of digital attenuator

Fig. 3. Resistance attenuation network topology

Fig. 4. The photograph of digital attenuator chip

Fig. 5. Measured input VSWR of all 64 states

Fig. 6. Measured output VSWR of all 64 states

Fig. 7. Measured insertion loss of reference state

Fig. 8. Measured relative attenuation of all 64 states

Fig. 9. Measured RMS error of attenuation of all 64 states

Fig. 10. Measured phase variation of all 64 states