Fig. 1. (Color online) Simplified CPT Cs atomic clock system.

Fig. 2. (Color online) The diagram of proposed FS-SoC system.

Fig. 3. (Color online) Overall structure of fractional-N CPPLL.

Fig. 4. (Color online) The phase noise curve of PLL.

Fig. 5. (Color online) The structure of 1PPS.

Fig. 6. Output driver schematic.

Fig. 7. (Color online) Output power of driver versus the Driver VDD.

Fig. 8. Power management structure.

Fig. 9. (a) Power detection basic structure. (b) Current summation schematic.

Fig. 10. Schematic diagram of power detector.

Fig. 11. (Color online) Conversion voltage versus the RF power.

Fig. 12. (Color online) Power stabilization loop diagram.

Fig. 13. Frequency domain model of PSL for stability analysis.

Fig. 14. (Color online) (a) KPOWER and (b) KPD versus output power. (c) Phase margin of PSL under different output power.

Fig. 15. (Color online) Chip micrographs of (a) the proposed FS-SoC, (b) power detector.

Fig. 16. (Color online) Measured RF signal phase noise of FS-SoC.

Fig. 17. (Color online) Chip phase noise consistency measurement.

Fig. 18. (Color online) Measured spectrum of RF signal.

Fig. 19. Measured 1PPS synchronization between the external 1 Hz signal and the on-chip 1 Hz signal.

Fig. 20. (Color online) Output power versus temperature with PD or without PD.