In the contemporary era of information exchange and global connectivity, accurate timing and clock synchronization play a pivotal role in facilitating seamless communication across diverse technology domains^[1]. Atomic clocks, renowned for their exceptional precision and frequency stability, are widely employed in satellite navigation systems, communication networks, and scientific measurements^[2−4]. Responding to the requirements of miniaturization and integration, atomic clocks based on coherent population trapping (CPT) demonstrate considerable potential in evolving into high-performance, compact, and low-power chip-scale atomic clocks (CSAC)^[5−11].

CPT atomic clocks utilize half of the hyperfine energy level frequency difference in the ground state of the atom as a frequency reference^[12]. Recent studies highlight that CPT-based chip-scale atomic clocks demonstrate short-term frequency stability of 10⁻¹¹τ−1/2 and mid-to-long-term frequency stability of 10⁻¹²τ−1/2^{[13, 14]}. The principal factor constraining the short-term frequency stability of CPT atomic clocks is the phase noise of the microwave signal, attributed to the Dick effect^{[15, 16]}. Moreover, fluctuations in the output power of the microwave signal introduce an off-resonant light shift, further impacting the mid-to-long-term frequency stability of CPT atomic clocks^{[17, 18]}. Addressing these influences is imperative for enhancing the overall performance of CSAC.

Moreover, global positioning system (GPS) satellites heavily rely on atomic clocks for precise timekeeping, facilitating the calculation of spatial coordinates such as latitude, longitude, and altitude by integrating data from multiple satellites^{[19, 20]}. Consequently, maintaining global time synchronization is crucial for effective satellite communications. One specific method employed for satellite clock synchronization is the one-pulse-per-second (1PPS) system^[21−23], which entails a satellite transmitting a pulse signal every second, and other satellites synchronizing their outputs to the same phase of this 1-s pulse signal. This synchronization ensures a consistent and accurate time reference among the satellites. Furthermore, beyond satellite communications, numerous applications, including smart power grids, demand precise clock synchronization. Therefore, the inclusion of a 1PPS module becomes essential for a comprehensive atomic clock system, catering to a wide range of synchronization requirements.

In this work, a 4.6 GHz frequency servo system-on-chip (FS-SoC) is proposed for miniaturized Cs atom CPT atomic clocks. To bolster the frequency stability of atomic clocks, an output power stabilization loop technology is introduced, effectively stabilizing the output power. As CPT atomic clocks continue to decrease in size, the integration of multifunctional systems on a chip becomes increasingly crucial. Acknowledging this trend, a power management system is integrated into the FS-SoC to ensure a robust power supply.

The simplified CPT Cs atomic clock system is illustrated in Fig. 1. A 4.6 GHz microwave signal modulates a laser with a wavelength (λ) of 894.6 nm, generating an upper and lower sideband coherent optical signal with a frequency difference of 9.2 GHz. This optical signal is utilized to induce CPT resonance within the atom cell. The transmitted light signal from the atom cell is subsequently captured by the photo detector. Through signal processing, the control voltage of the voltage-controlled crystal oscillator (VCXO) is corrected and stabilized. Once the CPT resonance signal is detected and both frequency feedback loops are locked, the VCXO inherits the frequency stability of the CPT resonance of the Cs atom.

A FS-SoC with PSL technology is presented, as illustrated in Fig. 2. The system employs a fractional-N charge pump phase-locked loop (CPPLL) to generate a 4.6 GHz RF signal for laser modulation. One pulse per second (1PPS) is utilized for GPS clock synchronization, which is driven by divide-4 signal from the 4.6-GHz VCO. Given the narrow linewidth of the detected CPT resonance signal with buffer gas 1 Hz–10 kHz^[13], a 35-bit delta-sigma modulator (DSM) with 0.291 mHz resolution is employed to identify the peak CPT response. Additionally, the modulation technique is superior to pure DC detection of the CPT resonance signal for a low noise spectrum density^[24], a 125-Hz frequency shift keying (FSK) modulation is implemented by utilizing an external 125-Hz square-wave input to periodically shift the frequency control word (FCW) of the DSM for microwave signal modulation. The lock detection circuit is used to detect whether the phase-locked loop is locked and gives a lock signal for CPT atomic clocks. Furthermore, a power management module is integrated to provide a clean and stable power supply for the FS-SoC. The off-chip power detector (PD) is responsible for detecting microwave output power and converting it to voltage for output power stabilization loop (PSL). The detailed design of both the FS-SoC and PD is elaborated below.

To ensure robust locking ability, the CPPLL is selected as the frequency synthesis loop^[25−30], as depicted in Fig. 3. A phase frequency detector (PFD) with controllable reset time is employed in this CPPLL for PVT insensitivity. Cascode current mirrors are applied in the charge pumps (CP) to minimize current mismatch, and complementary switches are employed to suppress the charge-sharing effect. Furthermore, four CP arrays are utilized to adjust the loop bandwidth and reduce in-band phase noise. A second-order loop filter (LF) is integrated to attenuate control ripple for a low reference spur. A class-B voltage-controlled oscillator (VCO) is employed to generate a 4.6 GHz signal due to its simple and robust structure^[31], with a 4-bit capacitive bank covering the 4.4–4.8 GHz RF signal range. A divider chain, which is controlled by the 35-bit MASH 1-1-1 DSM, is adopted to generated the divide signal with enhanced randomness and quantize noise shaping^{[32, 33]}. To clean accumulation jitter in the long divider chain, a retimer is inserted after divider chain. The output 4.6 GHz RF signal is divided by 4 using the prescaler to produce a 1.15 GHz signal for the 1PPS circuit. Moreover, the post-simulation phase noise contribution curve of each module in PLL is shown in Fig. 4.

1PPS second synchronization module is used in atomic clock to generate second pulse signal aligned with the rising edge of GPS second pulse. The structure block diagram of second synchronization module is shown in Fig. 5, which consists of four processes: synchronization, coarse alignment, fine alignment and pulse width trimming. First of all, the 10 MHz reference signal and GPS second pulse signal are synchronized by divide-4 signal from the 4.6 GHz VCO, respectively. A phase-shifting divider is implemented by counters and delay unit, which is used to divide the reference signal to the roughly-aligned 1 Hz signal with an error less than 100 ns. Then, the delay cell, which is driven by divide-4 signal from the VCO with a resolution of 1/1.15 GHz = 870 ps, finely adjusts the roughly-aligned 1 Hz signal using the phase error extracted by the PFD and the counter. Finally, the trim module reshapes the finely aligned signal with 400-μs pulse width.

An output driver is employed to amplify the PLL microwave signal, as depicted in Fig. 6. A microwave output power range of –3 to 3 dBm is necessary to drive the laser modulator, generating the first light sideband. The output power of the driver can be modified by adjusting the supply voltage, accomplished through a low drop-out regulator (LDO) with a variable output voltage, as detailed in the subsequent section.

The variations in driver output power with changes in (driver voltage-drain-drain) Driver VDD are illustrated in Fig. 7. The output power of the driver fluctuates from –6.9 to 4 dBm as Driver VDD ranges from 0.3 to 1 V.

A power management module is seamlessly integrated into the FS-SoC to ensure a clean and stable power supply, as depicted in Fig. 8. The current mode bandgap reference (CMBR) generates temperature-insensitive reference currents to serve as bias for the system modules. The LDO with an impedance-attenuated buffer reduces the output resistance of shunt feedback, which exhibits a good phase margin^[34]. There are four LDOs in the power management. Two LDOs with 1-V reference voltage supply power to the VCO and CP, PFD, Divider, DSM, 1PPS respectively. It is worth noting that the reference voltage of Driver VDD is determined by the digital-to-analog converter (DAC) control word, enabling control over the output power of the driver. Since the LDO of driver is related to the stability of the power stabilization loop, the design considerations for the LDO are given in the following sections. Moreover, DAC and VCXO are sensitive to the quality of power supply, a 3-V LDO is also integrated to provide clean power supply for DAC and VCXO. The error amplifier of the LDO is supplied by 3.3-V supply voltage. A p-metal-oxide-semiconductor (PMOS) is chosen as power metal-oxide-semiconductor field-effect transistor (MOSFET) for 3-V LDO. For the 1-V LDO, a n-metal-oxide-semiconductor (NMOS) is utilized to power MOSFET for fast response.

To achieve system output power detection and automatic regulation, a module with microwave power detection functionality is necessary. The root-mean-square (RMS) power detection method is employed, utilizing the V−I square law characteristic of MOSFET. The basic structure is illustrated in Fig. 9 (a). The circuit operates in the saturated region, and the input signal is assumed to be Vin=Vicosωt. Assuming no channel length modulation and short channel effect, we can derive Vout:

1Vout=VDD−Zload×12unCoxWL(VGS−VTH+Vicosωt)2.

Here Zload is composed of a low-pass filter composed of RC, when it filters out the RF signal and its second harmonic, it can be obtained:

2Vout=[VDD−Zload×12unCoxWL(VGS−VTH)2]−Zload×14unCoxWLVi2.

There is a reversed DC component of the RF signal in the Vout. The structure shown in Fig. 9 (b) is used to invert the DC component of the RF signal, and it has the function of current summation. Since the source bias voltages of the three MOSFET sources are different, they will be cut off in turn as the input voltage decreases.

The schematic diagram of the power detector is presented in Fig. 10. To achieve wideband input power detection, three saturated region RMS power detectors are arranged in parallel in the RF power detector to compensate for gain errors. As the input signal power increases, the input voltage of the current summer gradually decreases. The current-summing MOSFETs will cut off sequentially. The amplification of the DC component of the input signal will gradually decrease, resulting in an approximate logarithmic amplification effect. This configuration makes the power of the input signal proportional to the output voltage. The conversion voltage versus RF power is depicted in Fig. 11, illustrating that the conversion voltage changes almost linearly with RF power.

The fluctuation in microwave power is a primary factor contributing to the degradation of the frequency stability of CPT atomic clocks^[35]. Maintaining a stable microwave signal power is crucial for ensuring the frequency stability of atomic clocks. To address this, we propose an output power stabilization Loop (PSL) technology designed to stabilize the output power of the microwave signal, as illustrated in Fig. 12. In this process, the microwave signal power is initially detected by the power detector and converted into voltage. Subsequently, the error between the conversion voltage and the DAC control voltage is amplified by the error amplifier (EA), which outputs a voltage to serve as the reference voltage for the LDO to adjust the voltage of driver VDD. Ultimately, the PSL technology stabilizes the microwave output power.

The frequency domain model of the PSL is depicted in Fig. 13. The parameter KPOWER represents the small-signal gain of the voltage of driver VDD to the output power of the driver, ranging from 26.8 to 8.2 dB/V with an output power of –5 to 4 dBm, as shown in Fig. 14 (a). On the other hand, the poles of PD are at high frequencies, and the phase shift it causes in loop transmission could be negligible. KPD represents the small-signal gain of the output power to conversion voltage, varying from 0.0495 to 0.023 dB/V with an output power between –5 and 4 dBm, as illustrated in Fig. 14 (b). The error amplifier (EA) can be conceptualized as a unipolar point P1 with a DC gain Av2. The transfer function of the closed loop LDO can be written as T/(1+T), where T is the loop gain transfer function of LDO with two poles P2 and P3^[34], and can be given as:

3T=−Av2(1+SP2)(1+SP3).

The LDO is designed to be a single pole P2 within 1 MHz of the regulation loop unity-gain bandwidth, and 10×Av2×P2≈P3≈10MHz. So the transfer function of the closed loop LDO Tclose−loop can be approximately written as:

4Tclose−loop=−T1−T=Av2(1+SP2)(1+SP3)+Av2≈1(1+S0.12P3)(1+S0.88P3).

Based on the above, the loop gain transfer function of PSL is given as:

5TPSL=−KPDKPOWERAv1(1+S0.12P3)(1+S0.88P3)(1+SP1).

For PSL stability considerations, the value of Av1 and P1 are designed to be 60 dB and 1 kHz respectively. The Fig. 14 (c) shows the phase margin of PSL under different output power.

The proposed FS-SoC and PD are fabricated in the 65 nm CMOS process, the active areas of which are 1.71 and 0.16 mm² respectively as shown in Fig. 15. The proposed FS-SoC operates at a frequency range of 4.4 to 4.8 GHz, driven by a 10-MHz XO, while consuming only 19.7 mW of power.

For the phase noise performance, the output RF signal of FS-SoC is measured. At a frequency of 4.595 GHz, –69.5 and –83.9 dBc/Hz phase noise at 100 Hz offset and 1 kHz offset are achieved respectively as shown in Fig. 16, which improves the short-term frequency stability of CPT Cs atomic clocks. Additionally, the phase noise of five chips is measured, demonstrating excellent consistency, as shown in Fig. 17. Meanwhile, the output spectrum of RF signal is also given in Fig. 18, where the reference spur is –62 dBc and the fractional spur is –51 dBc.

As for the GPS clock synchronization, 1PPS is measured by synchronization between external 1 Hz signal and the on-chip 1 Hz signal, as shown in Fig. 19. The synchronization accuracy is less than 5 ns.

The RF signal output power versus temperature with PD or without PD is measured, as shown in Fig. 20. In practical applications, PD is individually packaged in a constant temperature chamber. The RF signal power varies by 1.6 dB without PD in the temperature range from –40 to 85 °C，and by 0.11 dB with PD. With the help of PSL technology, the RF output power is stabilized.

Table 1 shows the performance comparison with other CSAC. The Allan deviation of a Cs atomic clock using the proposed FS-SoC and PD is measured, which exhibits a better frequency stability of atomic clocks.

A 4.6 GHz frequency servo system-on-chip (FS-SoC) with power stabilization loop (PSL) technology is introduced for Cs atomic clocks and fabricated in the 65 nm CMOS process. The Cs atomic clock utilizing the proposed FS-SoC and PSL achieves an Allan deviation of 1.7×10−11 with a 1-s averaging time. This level of Allan deviation reflects the stability and precision of the chip scale atomic clock (CSAC), showcasing the effectiveness in improving frequency stability of atomic clocks.