Microelectronics, Volume. 53, Issue 4, 741(2023)

Design and Optimization of 12-kV SiC Planar Inversion MOSFET Using Shallow Trench N+ Injection in the JFET Region

ZHANG Bingke... LI Xuhan, WANG Rui, DONG Jiajun, CHANG Shucheng, SUN Junmin, BAI Xue, LI Zheyang and JIN Rui |Show fewer author(s)
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    References(17)

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    [16] [16] VUDUMULA P, KOTAMRAJU S. Design and optimization of 12-kV SiC planar inversion MOSFET using split dummy gate concept for high-frequency applications [J]. IEEE Transactions on Electron Devices, 2019, 66(12): 5266-5271.

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    ZHANG Bingke, LI Xuhan, WANG Rui, DONG Jiajun, CHANG Shucheng, SUN Junmin, BAI Xue, LI Zheyang, JIN Rui. Design and Optimization of 12-kV SiC Planar Inversion MOSFET Using Shallow Trench N+ Injection in the JFET Region[J]. Microelectronics, 2023, 53(4): 741

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    Paper Information

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    Received: May. 1, 2023

    Accepted: --

    Published Online: Jan. 3, 2024

    The Author Email:

    DOI:10.13911/j.cnki.1004-3365.230216

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