Acta Optica Sinica, Volume. 33, Issue 11, 1111001(2013)
Fast Lithography Simulation for One-Dimensional Layout
[1] [1] N B Cobb, A Zakhor. Fast sparse aerial-image calculation for OPC [C]. SPIE, 1995, 2621: 534-545.
[2] [2] Taichi Yamazaki, Ryohei Gorai, Yosuke Kojima, et al.. Attenuated phase-shift mask with high tolerance for 193 nm radiation damage [C]. SPIE, 2011, 8166: 81663V.
[3] [3] P Gupta, A B Kahng, S Nakagawa, et al.. Lithography simulation-based full-chip design analyses [C]. SPIE, 2006, 6156: 61560T.
[4] [4] B Charlotte, M Cement, B G Fabrice, et al.. Fully integrated litho aware PnR design solution [C]. SPIE, 2012, 8327: 83270A.
[5] [5] Cao Yuting, Wang Xiangzhao, Bu Yang, et al.. Analysis of mask shadowing effects in extreme-ultraviolet lithography [J]. Acta Optica Sinica, 2012, 32(8): 0805001.
[6] [6] D G Flagello, R J Socha, X Shi, et al.. Optimizing and enhancing optical systems to meet the low k1 challenge [C]. SPIE, 2003, 5040: 139-150.
[9] [9] ITRS, 2012 Update Overview of International Technology Roadmap for Semiconductors [Z]. 2012, 14.
[10] [10] M Lavin, F L Heng, G Northrop. Backend CAD flows for “restrictive design rules” [J]. Proceedings of the 2004 IEEE/ACM International Conference on Computer-Aided Design, 2004. 739-746.
[11] [11] V Kheterpal, V Rovner, T G Hersan, et al.. Design methodology for IC manufacturability based on regular logic-bricks [J]. Proceedings of the 42nd Annual Design Automation Conference, 2005, 353-358.
[12] [12] L Liebmann, L Pileggi, J Hibbeler, et al.. Simplify to survive: prescriptive layouts ensure profitable scaling to 32 nm and beyond [C]. SPIE, 2009, 7275: 72750A.
[13] [13] R T Greenway, R Hendel, K Jeong, et al.. Interference assisted lithography for patterning of 1D gridded design [C]. SPIE, 2009, 7271: 72712U.
[14] [14] M C Smayling, V Axelrad, K Tsujita, et al.. Sub-20 nm logic lithography optimization with simple OPC and multiple pitch division [C]. SPIE, 2012, 8326: 832613.
[15] [15] M C Smayling, V Axelrad. 32 nm and below logic patterning using optimized illumination and double patterning [C]. SPIE, 2009, 7274: 72740K.
[16] [16] C Bencher, H X Dai, Y M Chen. Gridded design rule scaling: taking the CPU toward the 16 nm node [C]. SPIE, 2009, 7274: 72740G.
[17] [17] Y C Pati, T Kailath. Phase-shifting masks for microlithography: automated design and mask requirements [J]. J Opt Soc Am A, 1994, 11(9): 2438-2453.
[18] [18] Y C Pati, A A Ghazanfarian, R F Pease. Exploiting structure in fast aerial image computation for integrated circuit patterns [J]. IEEE Transactions on Semiconductor Manufacturing, 1997, 10(1): 62-74.
[19] [19] Liu Shiyuan, Wu Xiaofei, Liu Wei, et al.. Fast aerial image simulations using one basis mask pattern for optical proximity correction [J]. J Vac Sci Technol B: Microelectronics and Nanometer Structures, 2011, 29(6): 06FH03.
[20] [20] Gong Peng, Liu Shiyuan, Lü Wen, et al.. Fast aerial image simulations for partially coherent systems by transmission cross coefficient decomposition with analytical kernels [J]. J Vac Sci Technol B: Microelectronics and Nanometer Structures, 2012, 30(6): 06FG03.
[21] [21] Cao Yuting, Wang Xiangzhao, Bu Yang. Fast simulation method for contact hole mask in extreme-ultraviolet lithography [J]. Acta Optica Sinica, 2012, 32(7): 0705001.
[22] [22] A K K Wong. Resolution Enhancement Techniques in Optical Lithography [M]. Bellingham, WA: SPIE Press, 2001. 58.
Get Citation
Copy Citation Text
Xie Chunlei, Shi Zheng, Lin Bin. Fast Lithography Simulation for One-Dimensional Layout[J]. Acta Optica Sinica, 2013, 33(11): 1111001
Category: Imaging Systems
Received: Apr. 2, 2013
Accepted: --
Published Online: Sep. 30, 2013
The Author Email: Chunlei Xie (xiecl@vlsi.zju.edu.cn)