[1] D Kim, J Alamo. 30-nm InAs PHEMTs With fT = 644 GHz and fmax = 681 GHz. IEEE Electron Device Letters, 31, 806-808(2010).

[2] R Lai, X B Mei, W R Deal et al. Sub 50 nm InP HEMT Device with fmax Greater than 1 THz, 609-611(2007).

[3] W R Deal, K Leong, A. Zamora, V Radisic et al. Recent progress in scaling InP HEMT TMIC technology to 850 GHz, 2014, 1-3.

[4] W Park, H Jo, H Kim et al. Terahertz In0.8Ga0.2As quantum-well HEMTs toward 6G applications, 11.4.1-11.4.4(2022).

[5] X B Mei, W Yoshida, M Lange et al. First Demonstration of Amplification at 1 THz Using 25-nm InP High Electron Mobility Transistor Process. IEEE Electron Device Letters, 36, 327-329(2015).

[6] H Jo, S Yun, J Kim et al. Sub-30-nm In0.8Ga0.2As Composite-Channel High-Electron-Mobility Transistors With Record High-Frequency Characteristics. IEEE Transactions on Electron Devices, 68, 2010-2016(2021).

[7] K J Chen, T Enoki, K Maezawa et al. High-performance InP-based enhancement-mode HEMTs using non-alloyed ohmic contacts and Pt-based buried-gate technologies. IEEE Transactions on Electron Devices, 43, 252-257(1996).

[8] K Shinohara, Y Yamashita, A Endoh et al. 547 GHz fT In0.7Ga0.3As-In0.52Al0.48As HEMTs with reduced source and drain resistance. IEEE Electron Device Letters, 25, 241-243(2004).

[9] Ruize Feng, Bo Wang, Shurui Cao et al. Impact of symmetric gate-recess length on the DC and RF characteristics of InP HEMTs. Chinese Physics B, 31, 018505(2022).

[10] T Takahashi, K Makiyama, N Hara et al. Improvement in high frequency and noise characteristics of InP-based HEMTs by reducing parasitic capacitance, 1-4(2008).

[11] D Kim, J Alamo, J Lee et al. The Impact of Side-Recess Spacing on the Logic Performance of 50 nm InGaAs HEMTs, 177-180(2006).

[12] M Samnouni, N Wichmann, X Wallart et al. 75 nm Gate Length PHEMT With fmax = 800 GHz Using Asymmetric Gate Recess: RF and Noise Investigation. IEEE Transactions on Electron Devices, 68, 4289-4295(2021).

[13] K Shinohara, P S Chen, J Bergman et al. Ultra-High-Speed Low-Noise InP-HEMT Technology, 337-340(2006).

[14] T Suemitsu, H Yokoyama, Y Umeda et al. High-performance 0.1-µm-gate enhancement-mode InAlAs/InGaAs HEMT’s using two-step-recessed gate technology. IEEE Transactions on Electron Devices, 46, 1074-1080(1999).

[15] T Kim, D Kim, S Park et al. A Two-Step-Recess Process Based on Atomic-Layer Etching for High-Performance In0.52Al0.48As/In0.53Ga0.47As p-HEMTs. IEEE Transactions on Electron Devices, 55, 1577-1584(2008).

[16] Peng Ding, Chen Chen, Wuchang Ding et al. Ultra-thin 20 nm-PECVD-Si3N4 surface passivation in T-shaped gate InAlAs/InGaAs InP-based HEMTs and its impact on DC and RF performance. Solid-State Electronics, 123, 1-5(2016).

[17] G Dambrine, A Cappy, F Heliodore et al. A new method for determining the FET small-signal equivalent circuit. IEEE Transactions on Microwave Theory and Techniques, 36, 1151-1159(1988).

[18] M Asif, D Peng, C Chen et al. Analysis of Passivation Techniques in InP HEMTs and Implementation of an Analytical Model of fT Based on the Small Signal Equivalent Circuit. Journal of Nanoscience and Nanotechnology, 19, 2537-2546(2019).

[19] T Takahashi, Y Kawano, K Makiyama et al. Enhancement of fmax to 910 GHz by Adopting Asymmetric Gate Recess and Double-Side-Doped Structure in 75-nm-Gate InAlAs/InGaAs HEMTs. IEEE Transactions on Electron Devices, 64, 89-95(2017).

[20] Guo Zhou, Yingsheng Bi, Zhuo Chen et al. Preparation and Performances of InP HEMT Device with Cavity Gate Structure. Semiconductor Technology.

[21] Lisen Zhang, Zhihong Feng, Dong Xing et al. 70 nm gate-length THz InP-based In0.7Ga0.3As/In0.52Al0.48As HEMT with fmax of 540 GHz, 1-4(2014).