Fig. 1. The EBL process for T-gate fabrication and small gate recess (The layers below the InP etch-stopped layer are not shown)

Fig. 2. SEM image of the cross section of the fabricated device with the whole small recess toward source（type B），where the large gate recess was measured about 500 nm and the small recess was measured about 100 nm

Fig. 3. Partial DC and RF characteristics of InP HEMT：(a) DC characteristics of the InGaAs/InAlAs HEMTs with the whole small recess offset, and (b) the measured transconductance (g_m) of the devices as a function of I_DS, for the value of V_DS = 0.8 V (L_g = 80 nm, W_g = 50 µm × 2 )

Fig. 4. Dependence of DC drain conductance on applied V_DS with different structures

Fig. 5. Measured (symbols) and small-signal modeled (lines) RF gains [ |h₂₁|, U and maximum available gain (MAG/MSG) ] versus frequency with the L_g = 80 nm InGaAs/InAlAs HEMTs . The offsets from large recess center were 0.0 µm (type A), - 0.1 µm (type B), and + 0.1 µm (type C). The bias conditions were near the g_m peak gate voltage and at V_DS = 0.8 V

Fig. 6. Extracted f_T against I_DS of L_g = 80 nm InGaAs/InAlAs HEMTs at V_DS = 0.8 V with different structures