In conclusion, we report a monolithic O-band 4λ × 64 Gb/s optical transceiver, which achieves the aggregated bandwidth up to 256 Gb/s for the optical I/O. Experimental results show that the complete TX and RX consume 2.85 pJ/bit power, reaching 10^–12 pre-forward error correction (FEC) BER. In addition to this work, we have also achieved a monolithically integrated EPIC transceiver based on a Mach-Zehnder modulator for ethernet co-packaged optics (CPO), which will be reported in the near future.

The optical response of the TX is exhibited in Fig. 2, where an extinction ratio (ER) of more than 15 dB and a free spectral range (FSR) of 9.2 nm is measured. The RX has a FSR of 9.2 nm and ER greater than 8 dB. To demonstrate the high-speed performance, an arbitrary waveform generator (AWG) is used to input differential signals into the transceiver link. The output signals are then collected and analyzed to generate eye diagrams using a digital communication analyzer (DCA). Fig. 3 shows the 64 Gb/s not return to zero (NRZ) transmission diagram of TX. An open eye with modulation ER of ~7 dB is obtained. The 64 Gb/s NRZ eye diagram of RX under an input optical power OMA of –5 dBm is also shown in Fig. 3. The TIA output voltage swing is 38 mV and the jitter is 1.2 ps. It should be noticed that, a 5-tap feed forward equalization (FFE) is applied to compensate for the PCB trace and connnector loss (~5 dB at 40 GHz in this work) at the TX input and the RX output, respectively, which is typically much smaller in a xPU package and would be provided by the xPU SERDES in the real application. With the WDM technology, 4-channel arrays aggregatetotal data rates of 256 Gb/s both in the transmitter and receiver (BER < 10^–12) with the energy efficiency of 1.6 and 1.25 pJ/b, respectively. Table 1 shows a comparison of this performance with other reports state-of-the-art^[9−13]. Our work achieves the advantages of higher channel data rates, lower power consumption and higher modulation ER.

With the explosive development of artificial intelligence (AI), machine learning (ML), and high-performance computing (HPC), the ever-growing data movement is asking for high density interconnects with higher bandwidth (BW), lower power and lower latency^[1−3]. The optical I/O leverages silicon photonic (SiPh) technology to enable high-density large-scale integrated photonics. In this way, the miniaturized optical transceiver could be moved into the xPU package and directly attached to the fiber at chip edge. The optical I/O extends the electrical die-to-die links to tens of meters, which scales-out the highly parallel computing system with high energy efficiency. Previously, the photonics and electronics are fabricated in different process and realized in separate chips, which is then integrated through packaging (2D, 2.5D or 3D)^{[4, 5]}. However, the inevitable electrostatic discharge (ESD) protection circuits and bond-pads introduce comparable capacitance to the main photonic devices, which deviates the signal integrity and consumes significant power. In addition, the limited number of bond wires or bumps cannot support large-scale high-density chiplet integration. Herein, we present a monolithic 4λ × 64 Gb/s SiPh transceiver in a single 45 nm SOI-CMOS^{[6, 7]} electronic−photonic integrated chip (EPIC)^[8]. By integrating all the photodetector (PD), micro-ring resonator (MRR) based modulators and filters, together with co-designed CMOS drivers, transimpedance amplifiers (TIAs) and wavelength thermal-control units (TCU), extremely high BW-density and power efficiency is demonstrated with the aid of external laser sources. Experimental results show the proposed EPIC consumes only 1.6 and 1.25 pJ/bit in the optical transmitter (TX) and receiver (RX), respectively. The O-band wavelength division multiplexing (WDM) aggregates a total data rate of 256 Gb/s and achieves the bit-error rate (BER) lower than 10⁻¹².

Fig. 1 shows the micrograph of the EPIC and monolithically integrated optical transceiver details. The photonic components consist of the MRR based modulators (MRM) and filters with around 7.5 μm radius, and the integrated TCU are used to tune the resonant wavelengths. As depicted in the single-channel TX system diagram, to compensate for channel losses from the printed circuit board (PCB), a continuous time linear equalizer (CTLE) provides up to 10 dB equalization at25 GHz. A 2-stage variable gain amplifier (VGA) is employed to provide 15 dB adjustable range to cover larger input dynamic range. A dual-rail outputs pre-driver is designed to generate dual paths working at separated voltage domains (0–1 V and 1–2 V). By driving the final stage in a stacked push−pull manner, the output voltage swing is doubled to 2.5 V_ppd. The differential outputs are AC coupled to the MRM with proper DC-bias on the PN-junction for the depletion mode operation. Moreover, to improve the linearity when driving a capacitive MRM, 500 Ω resistive back-termination is adopted between the differential outputs, which at the same time minimizes the impedance fluctuation of the modulated MRM capacitance^[8]. The optical receiver employs four MRR filters cascaded on the bus waveguide, which select the corresponding wavelength signals at each MRR’s resonate frequency. At each MRR's downstream port, a Ge-Si photodetector converts the high-speed optical power into photocurrents, which are then amplified in the TIA. As shown in the receiver system block diagram of Fig. 1, after amplification, the signal then passes the signal to differential (S2D) converter, which provides differential output to suppress the common-mode noise. To eliminate the DC drift induced by the variation of input average optical power, a DC offset cancellation loop (DCOL) is implemented at the input node to shunt the additional current to ground. Meanwhile, to compensate for the inter-symbol interference (ISI) caused by the MRR bandwidth limitation, multi-stage source degenerated equalization are utilized in both the VGA and the last driving stage, offering up to 8.5 dB of equalization capability^[8]. Fig. 1 also shows the microscopic image of the EPIC, while the area of the TX is 870 × 1500 μm² and the RX is 640 × 1500 μm².