Fig. 1. (Color online) (a) The dependences between the breakdown field and bandgap. (b) Theoretical limits of the relation between on-resistances and breakdown voltage for major semiconductors and β-Ga₂O₃. © 2012 American Institute of Physics. Reprinted with permission from Ref. [6].

Fig. 2. (Color online) (a) The schematic of the showerhead MOCVD reaction chamber. © 2021 Elsevier B.V. Reprinted with permission from Ref. [34]. (b) The schematic diagram showing the mechanism of step-flow growth and two-dimensional nucleation growth. © 2019 American Institute of Physics. Reprinted with permission from Ref. [37].

Fig. 3. (Color online) (a) Temperature dependence of carrier mobility tested in low-temperature hall measurement. (b) SIMS depth distribution of impurities in MOCVD grown β-Ga₂O₃ epitaxial layer on (010) substrate. © 2019 American Institute of Physics. Reprinted with permission from Ref. [31].

Fig. 4. (Color online) (a) Fabrication process and (b) the geometry structure false-colored SEM image of FinFET with an L_SD = 4. (c) The transfer characteristics in the form of log(I_D)–V_G with the forward and reverse sweeps. (d) The breakdown characteristics of β-Ga₂O₃ FinFETs with L_GD of 16 and 21 μm measured at V_GS = 0 V. © 2016 Chabak et al. Reprinted with permission from Ref. [40].

Fig. 5. (Color online) (a) The false-colored SEM view of a recessed gate device with the L_SD = 3 µm device. The HR-TEM picture below shows the facet morphology of sidewall and bottom in the gate-recess contact and gate metal interfaces. (b) The output characteristics for an L_SD = 8 µm device at the gate bias of 8 V. (c) Linear transfer characteristics at V_DS = 15 V. © 2017 IEEE. Reprinted with permission from Ref. [29].

Fig. 6. (Color online) (a) Schematic diagram of the enhancement-mode MOSFET. (b) Linear transfer characteristics (I_DS–V_GS) of the fabricated trench gate MOSFET measured at V_DS = 10 V. © 2019 IEEE. Reprinted with permission from Ref. [42].

Fig. 7. (Color online) (a) Cross section view of the E-mode MOSFETs with the UID channel layer and Si⁺-implanted source (drain) contacts. (b) Linear transfer characteristics at V_DS = 15 V. © 2017 The Japan Society of Applied Physics. Reprinted with permission from Ref. [47].

Fig. 8. (Color online) Schematic diagram of lateral Ga₂O₃ MOSFET structures (a) without and (b) with UID buffer layer. (c) The novel triple layer design of lateral MOSFET structure. © 2021 IEEE. Reprinted with permission from Ref. [47].

Fig. 9. (Color online) Cross section view of the FET with (a) UD layer and (b) VLD layer. The (c) linear and (d) semi-logarithmic scale of transfer characteristics extracted from the simulation. © 2021 IEEE. Reprinted with permission from Ref. [48].

Fig. 10. (Color online) (a) Schematic diagram of the OA β-Ga₂O₃ MOSFET with L_gd = 17 μm. (b) Log-scale transfer characteristics of the device. (c) The breakdown characteristics of the OA Ga₂O₃ MOSFET without source field plate, with single SFP and with double SFP. © 2019 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim. Reprinted with permission from Ref. [50].

Fig. 11. (Color online) Cross-sectional view of the E-mode HJ-FET (a) without the Al₂O₃ layer and (b) with the Al₂O₃ layer. The linear-scale transfer characteristics for the E-mode HJ-FET (c) without the Al₂O₃ layer and (d) with the Al₂O₃ layer. © 2022 IEEE. Reprinted with permission from Ref. [55].

Fig. 12. (Color online) (a) Cross-section view of the gate-recessed HJ-FET. (b) Log-scale I_DS–V_GS curves of the gate-recessed HJ-FET at V_DS of 0.1, 5, and 8 V. © 2022 IEEE. Reprinted with permission from Ref. [30].

Fig. 13. (Color online) (a) Schematic diagram of L-FeG Ga₂O₃ MOSFET. (b) Linear-scale I_DS–V_DS and (c) I_DS–V_GS curves of the D- and E-mode L-FeG Ga₂O₃ MOSFET with an L_SD = 11.4 μm © 2020 Feng et al. Reprinted with permission from Ref. [30].

Fig. 14. (Color online) Cross-sectional view of the current aperture vertical Ga₂O₃. © 2018 IEEE. Reprinted with permission from Ref. [57].

Fig. 15. (Color online) Schematics of (a) E-mode and (b) D-mode current aperture vertical Ga₂O₃ MOSFETs. © 2019 IEEE. Reprinted with permission from Ref. [58].

Fig. 16. (Color online) Cross-section schematic of the fabricated VDBFET. © 2022 IEEE. Reprinted with permission from Ref. [59].

Fig. 17. (Color online) (a) Cross sections view and (b) optical micrograph of a Ga₂O₃ UMOSFET with CBL realized by oxygen annealing. (c) Transfer and (d) output characteristics of Ga₂O₃ UMOSFET © 2022 Zhou et al. Reprinted with permission from Ref. [60].

Fig. 18. (Color online) (a) Schematic view of Ga₂O₃ UMOSFET with CBL realized by N⁺ implantation. Output characteristics of (b) UMOS-LN and (c) UMOS-HN. Three terminal breakdown characteristics of (d) UMOS-LN and (e) UMOS-HN. © 2023 IEEE. Reprinted with permission from Ref. [61].

Fig. 19. (Color online) (a) Cross sections view and (b) output characteristics of a Ga₂O₃ FinFET. © 2018 IEEE. Reprinted with permission from Ref. [62].

Fig. 20. (Color online) Cross section view of (a) gate-connected Ga₂O₃ FP-MOSFET. © 2015 IEEE. (b) SFP-MOSFET © 2018 IEEE. (c) Composite gate-connected Ga₂O₃ FP-MOSFET © 2018 IEEE. (d) Ga₂O₃ composite field plate MOSFET © Mun et al. 2019. (e) Composite gate-connected Ga₂O₃ FP-MOSFET with polymer passivation. © 2020 IEEE.

Fig. 21. (Color online) (a–e) Schematic of the fabricating steps for β-Ga₂O₃ SJ-equivalent MOSFETs. (f) The Photographs of SJ formed by parallel arranged p-NiO/n-Ga₂O₃ strips in the region between gate and drain. (g) 3-D schematic diagram of the β-Ga₂O₃ SJ-equivalent MOSFETs. © 2022 IEEE. Reprinted with permission from Ref. [67].

Fig. 22. (Color online) (a) Schematic diagram of the β-Ga₂O₃ MOSFET. (b) CCD images of β-Ga₂O₃ MOSFETs with four different channel orientations. (c) Simulation and experimental results of Gate temperatures and IR images for MOSFETs with different orientations. (d) Simulated results of relation between MOSFET channel temperatures and channel orientation at V_GS = 4 V. Two devices with different channel widths of 50 and 100 μm were used in this simulation. © 2022 IEEE. Reprinted with permission from Ref. [71].

Fig. 23. (Color online) (a) Option 1: Cross section view of a lateral β-Ga₂O₃ MOSFETs. (b) Option 2: A simulated structure with the β-Ga₂O₃ substrate bonded by the diamond at the bottom. (c) Option 3: A simulated structure based on the option 2 in (b) optimized by depositing the polycrystalline diamond over the exposed part of β-Ga₂O₃ channel layer. © 2022 IEEE. Reprinted with permission from Ref. [72].