[1] [1] Rice J E. An overview of fault models and testing approaches for reversible logic ［C］. Communications, Computers and Signal Processing (PACRIM), 2013 IEEE Pacific Rim Conference on IEEE, 2013, 125-130.

[2] [2] Patel K N, Hayes J P, Markov I L. Fault testing for reversible circuits ［J］. IEEE Transactions on Computer-Aided Design, 2004, 23(8): 1220-1230.

[3] [3] Sen B, Das J, Sikdar B K. A DFT methodology targeting online testing of reversible circuit ［C］. Devices, Circuits and Systems (ICDCS), 2012 International Conference on IEEE, 2012, 689-693.

[4] [4] Wille R, Zhang H, Drechsler R. Fault ordering for automatic test pattern generation of reversible circuits ［C］. Multiple-Valued Logic (ISMVL), 2013 IEEE 43rd International Symposium on IEEE, 2013, 29-34.

[5] [5] Kole D K, Rahaman H, et al. Derivation of optimal test set for detection of multiple missing-gate faults in reversible circuits ［C］. th IEEE Asian Test Symposium, 2010.

[6] [6] Zhang H, Wille R, Drechsler R. Improved fault diagnosis for reversible circuits［C］. Test Symposium (ATS), 2011 20th Asian. IEEE, 2011, 207-212.

[8] [8] Barenco A, Bennett C H, Cleve R, et al. Elementary gates for quantum computation ［J］. Am. Phys. Soc., 1995, 52(5): 3457-3467.

[9] [9] Wille R, Lye A, Drechsler R. Considering nearest neighbor constraints of quantum circuits at the reversible circuit level ［J］. Quantum Information Processing, 2013, 13(2): 185-199.

[10] [10] Zhong J, Muzio J C. Analyzing fault models for reversible logic circuits ［C］. IEEE Congress on Evolutionary Computation, 2006, 2422-2427.

[11] [11] Maslov D. Reversible logic synthesis benchmarks page ［OL］. http://webhome.cs.uvic.ca/dmaslov/.