Magnetic random-access memory (MRAM), especially spin-transfer torque (STT) MRAM has already emerged into the consumer market. It is considered as a promising candidate for “edge” applications such as AI, IoT, and etc.^[1−3]. Major semiconductor foundries like TSMC^[4−6], GlobalFoundries^[7−10], Samsung^[11−13], one after another announced mass production of the embedded STT-MRAM, replacing embedded NOR flash (eFlash) below the 28 nm complementary metal oxide semiconductor (CMOS) technology node. The overall performances of the embedded STT-MRAM, including operation voltages, write/read speeds, endurance, feature sizes etc. surpass those of the eFlash^[14]. Additionally, great efforts are being made in the MRAM industry to develop STT-MRAM as a working memory^[15−17]. IBM, for instance, introduced a 14 nm FinFET-based STT-MRAM macro in 2020 for last level cache (LLC) applications^[17]. Although the write speed can be reduced to 4 ns, the endurance of the STT-MRAM still falls short of meeting the requirements for the SRAM replacement in LLC application, where write speed must be under 2 ns and endurance should exceed 10¹⁷ cycles^[18].

To overcome the challenges faced by the STT-MRAM, spin-orbit torque (SOT) MRAM has emerged as a promising alternative^[19−24]. This is because SOT-MRAMs feature high endurance and fast switching speed, thanks to the separation of read/write current paths^[25−29] and less incubation time during the write operations^[30], distinguishing them from the STT-MRAM^[31]. Researchers and industry players have made significant progress in realizing SOT-MRAM technology^[32−43]. For instance, Beihang University first implemented the interplay of STT and SOT in the write operations, addressing the field-free issue for “type-Z” devices^[32]. IMEC first demonstrated field-free perpendicular MTJs (referred to as “type-Z” device) in a 300 mm wafer, utilizing an additional magnetic hard mask layer^[34]. Tohoku University showcased a 4 KB SOT-MRAM using canted in-plane MTJs^[37]. TSMC, in collaboration with ITRI, also successfully delivered an 8 Kb SOT-MRAM array (“type-Y” devices)^{[38, 39]}. However, it is important to note that the SOT-MRAM is still in the research and development (R&D) phase worldwide. This is because various challenges persist, such as integration process, switching efficiency, field-free switching, and more, requiring substantial efforts for resolutions^{[44, 45]}.

In our previous work, we successfully integration isolated SOT-MTJs in a 200 mm-wafer R&D platform, achieving uniform electrical and magnetic performance across the wafer^[46]. In addition, high endurance of up to 10¹² cycles was achieved for the fabricated isolated SOT-MTJs^{[28, 46]}. Building upon this achievement, we further integrated the SOT-MTJs into an array in conjunction with CMOS in the 200 mm wafer. We finally succeed in demonstrating of the 1 Kb SOT-MRAM multiplexer (MUX) array, with competitive specifications over all the reported works. For the 1 Kb SOT-MRAM MUX array, several aspects should be considered simultaneously: (1) excellent fabrication process to ensure devices with good morphology and stable performance^[47]; (2) tight distribution of high and low resistance within the array^[39]; (3) a large TMR value to provide a sufficient reading window^[8]; (4) industrial-grade operation temperature capability to meet the practical applications requirements^{[25, 41]}. Thus, following the fabrication of the SOT-MRAM MUX array, we systematically characterized the electrical properties, with a particular focusing on the write operation capabilities under industry-grade temperatures.

We will first briefly introduce the physical properties of the 1 Kb SOT-MRAM MUX array. The most critical SOT-MTJ stacks were deposited in a specialized PVD consisting of (from the bottom to the top) CMOS substrate/β-W (5)/CoFeB (1.3)/MgO (1.5)/CoFeB (1.9)/CoFe (0.8)/Ru (0.8)/CoFe (2.5)/IrMn (7.5)/Ta (3)/Ru (2)/Ta (2). The numbers in parentheses signify every layer thickness in nanometer. Each layer thickness nonuniformity (sigma%) is smaller than 2% across the wafer confirmed through the 49 points resistivity measurements. We keep monitoring the film thicknesses periodically to ensure 2% of wafer-to-wafer variations. Overall film stacks, especially for the MgO tunneling barrier/CoFeB interfaces, are well stacked with sharp interfaces confirmed by the TEM^[46] thanks to the surface treatment by the chemical mechanical polishing process. Detailed information of the integration procedures and isolated device performance can be found in ourprevious work^[46]. Fig. 1(a) shows a top-view image of the 1 Kb MUX array taken from an optical microscope. The actual physical size of the MUX array in the picture does not exceed 1 × 1 mm². As shown in Fig. 1(b), the 1 Kb SOT-MRAM MUX array includes a row address decoder, a column address decoder, SOT-MTJ arrays, and a MUX circuit. Through the cooperation of the MUX circuit and the address decoders, SOT-MTJs of all addresses can be accessed and tested by external analog signals. Fig. 1(c) shows a magnified image of the MUX array after the MTJ etch process, which was captured using a scanning electron microscope (SEM). The MTJs in the SEM image are patterned into “type-Y” devices^[48] having an elliptical shape. Although the “type-Y” SOT-MTJ devices have lower density and limited scalability compared to the “type-Z” devices, they do have some advantages^[25], including: (1) the in-plane MTJ stacks for the “type-Y” devices are relatively easier to be deposited with sufficient pinning field as compared with those of the top-pinned perpendicular MTJ stacks for the “type-Z” devices; (2) “type-Y” devices show deterministic switching without the need for an additional bias field to break the symmetry, resulting in a less-complexity integration process. The designed critical dimensions (CD) of the MTJs in the MUX array are 300 nm for the short axis a and 1050 nm for the long axis b, with an aspect ratio (b/a) of 3.5. As can be seen from Fig. 1(c), the MTJs are well distributedwith an excellent within-array CD sigma% (standard deviation/average value) around 1%. Fig. 1(d) shows a cross-section transmission electron microscope (TEM) image of a selected SOT-MTJ from the fully integrated 200 mm CMOS wafer. The front-end of line (FEOL) and back-end of line (BEOL) processes of the 200 mm CMOS wafer adopt a standard 180 nm CMOS technology node process from a common foundry. After completing the “Metal 5” and “Via 5”, the wafer was transferred to a dedicated MRAM R&D process platform. The SOT-MTJs are integrated between the “Metal 5” and the passivation layer. The height of the SOT-MTJs (including the metal hard mask for the top electrode connection) totals approximately 100 nm. With such height, the SOT-MTJs can be potentially moved downward even to “Metal 1” in the near future, which is close to the transistors and enable faster write/read operation speeds.

Following the integration of the MUX array, the electrical properties of the 1 Kb SOT-MRAM MUX array were systematically investigated. An external bias voltage VDD of 3.3 V was applied to the chip to select each SOT-MTJ bit within the MUX array. Another tunable bias voltage was applied to drive the read/write operations of the selected SOT-MTJ. We initiated the study of the analog read tests to evaluate the magnetoresistances of the SOT-MTJs within the MUX array. The tunneling magnetoresistance (TMR) ratio is defined as (R_AP − R_P)/R_P, where R_AP and R_P are the tunneling resistances measured at 100 mV for both antiparallel (AP) and parallel (P) magnetization configurations between the top and bottom magnetic layers. Subsequently, we conducted statistical analysis to assess the write operation capabilities of the MUX array. This includes evaluating the write error rate (WER), and examining the write shmoo under various bias voltages and pulse widths. Furthermore, the temperature dependence of the analog read results and write capabilities were investigated over a wide temperature range from −40 to 125 °C.

We will first introduce the analog read results obtained from the SOT-MRAM MUX array. The R_P and R_AP were measured after the SOT-MTJs were set to either the P or AP states under appropriate write bias voltages. Fig. 2(a) shows the quantile plot of the R_P and R_AP recorded for all the bits in the 1 Kb MUX array. The R_P and R_AP were normalized to the average value of the R_P in the 1 Kb MUX array. As illustrated in Fig. 2(a), the R_P values exhibit normal distributions with a tight R_{P_}sigma% of 3.9%, aligning well with the CD distributions as described above. Fig. 2(b) presents the correlation between the TMR and the R_P. No clear resistance open and/or short bits are found among the SOT-MTJs within the 1 Kb MUX array as indicated in Fig. 2(b). This finding confirms the well-controlled and robust process employed in our MRAM R&D platform. Additionally, the majority of the SOT-MTJs exhibit TMR values above 80%. Although this value is slightly lower than that of 100% film level TMR obtained by current in-plane tunneling technology (CIPT)^[46], it can be attributed to potential extrinsic defects at the magnetic layer/MgO interfaces or the sidewall damage of the MTJs caused by the subsequent process. However, it is worth noting that the ratio of TMR/R_P_sigma% is 21.4. This implies that the R_P and R_AP are well separated with a wide gap of 21.4 R_{P_}sigma. Despite the 1 Kb MUX array exhibiting relatively lower TMR ratios of around 80%, such a wide gap will ensure enough read margin even if we use a middle-point sense amplifier circuit design^[49]. Nevertheless, by optimizing the MTJ film stacks and integration processes in the future, it is possible to further enhance the TMR ratios to approximately 200%^[45].

Next, we characterized the WER for the SOT-MTJs in the MUX array. Fig. 3(a) shows typical WER curves as a function of bias voltages for a write pulse width of 100 ns, where positive bias voltage corresponds to the write AP direction and negative bias voltage corresponds to the write P direction. Each data point in Fig. 3(a) represents the write failure rate for a selected device tested over 1 million cycles under a constant bias voltage. Every cycle consists of a sequence of reset-read-write-read operations. The bias voltages were normalized to the median switching voltage of 1.25 V at WER = 10⁻⁴. As observed in Fig. 3(a), the WER curves exhibit a smooth and sharp decrease, successfully achieving relatively symmetrical WER level of 10⁻⁶ for both the write P and AP directions. In addition, the bias voltages at WER = 10⁻⁶ are only about 10% higher than those at WER = 10⁻⁴. Due to the test time limitations, we only collected WER curves down to 10⁻⁴ level for over 70 devices from the MUX array, as displayed in Fig. 3(b). Similar to Fig. 3(a), all WER curves show reliable switching down to 10⁻⁴ level at a write pulse width of 100 ns. Most importantly, we do not observe ballooning effects^[50] or back-hopping behaviors^{[50, 51]} in the obtained WER curves for both write directions across all the measured devices. This suggests that the SOT-MTJs feature robust and reliable switching behaviors when tested under a 100 ns pulse width. Moreover, the sigma of the bias voltage at WER = 10⁻⁴ is 0.16 V with sigma% of 12.8% for the bias voltage distribution. This distribution is reasonably favorable for a small density array, such as Kb-level array. However, it would be relatively large for a larger Mb-level array. This arises from the fact that, in order to have sub-parts-per-million (ppm) level bit error rate (BER) for a Mb array, an operation voltage V_OP = V_median + 5 V__sigma is necessary to be applied. Here V_OP is the operation voltage, V_median and V__sigma are the median voltage and the sigma of the voltage at sub-ppm-level WER, respectively. If the V__sigma is large, the value of the V_OP would be large and exceed the operation margin, even if the V_median are the same. There are several factors that would contribute to these relatively large distributions. First, we observe that the sigma% of the bias voltages are much larger than those of the CD and magnetic free layer thickness of the SOT-MTJs within the MUX array. This suggests that the CD and magnetic free layer thickness are not the main root causes. Then, it is likely that these distributions could be attributed to (1) the extrinsic defects inside of the magnetic free layer, and/or (2) non-uniform spin current generated from the SOT heavy metal layer or injected into the ferromagnetic layer due to the imperfect quality of the interfaces between the heavy metal and magnetic free layer. To address these issues, further engineering of the integration process is necessary, including optimizing the quality of the SOT material and the magnetic free layer, and implementing damage-free MTJ etching techniques in the future studies.

Then, we checked the temperature dependence of the aforementioned electrical parameters of the MUX array across an industry-grade temperature range from −40 to 125 °C. We measured the R_AP and R_P distributions of the array devices at different temperatures and calculated the TMR. Fig. 4(a) illustrates the TMR ratios as a function of the temperature. The median values of the TMR ratios decrease from 96% at –40 °C to 59% at 125 °C, which shows a consistent trend with previous works^{[49, 52]}. Although the TMR drops by nearly half, it would remain sufficient for automotive applications when employing differential-reference or self-reference sense amplifier circuit designs. However, it is still necessary to achieve as high TMR ratios over 100% as possible at high temperatures such as 160 °C to meet low read errors and fast read speed^{[53, 54]} and to reduce the overhead of circuit design. The TMR ratios could be improved through careful design of the film stack and optimization of the PVD deposition conditions, such as gas, power, chamber configurations, etc.

Figs. 4(b) and 4(c) summarize the critical switching current densities of the MUX array as a function of the temperature from different perspectives. The critical current densities are defined as the values at the 50% switching probabilities for AP-to-P and P-to-AP directions, obtained from R−V measurements under 100 ns pulse width for all the SOT-MTJs in the MUX array. The values in both Figs. 4(b) and 4(c) are normalized to the median critical current density J_C = 19 MA/cm² at 25 °C. As illustrated in Fig. 4(b), the current densities slightly increase by 5% at −40 °C as compared to that at 25 °C. Fig. 4(c) presents the cumulative distribution function (CDF) of the critical switching current densities calculated from the data in Fig. 4(b). The current densities at each temperature follow normal distributions and are tightly distributed with sigma% values of 9.1%, 9.0%, and 10.8% for −40, 25, and 125 °C, respectively. The sigma% values are similar between −40 and 25 °C and are lower than that of the 125 °C. This suggests that the magnetic properties at −40 and 25 °C are similar, resulting in only minor changes of switching current density. However, at 125 °C, the thermally induced fluctuations contributed to an overall reduction in the switching current density while enlarging the sigma% value.

Based on the above results, we then examined the write capability of the MUX array through the write shmoo tests. Figs. 5(a)−5(c) are the write shmoo plots at different temperatures for the P-to-AP direction, while Figs. 5(d)−5(f) are the corresponding ones for the AP-to-P direction. These shmoo plots show the write failure rates of 1 Kb in the MUX array at various write speeds (x-axis) and write bias voltages (y-axis). The pulse widths range from 20 to 200 ns and the bias voltages vary from 0.2 to 1.8 V. The write failure rates are presented using a color gradient, with the scale bar shown on the right: red indicates a 100% fail rate, while blue represents zero fail. From Figs. 5(b) and 5(e), it is evident that the write failure rates tested at 25 °C exhibit a distinct horizontal boundary between the red and the blue regions around write bias voltage of approximate 1 V. This suggests that the write failure rates are primarily influenced by the write bias voltages rather than the pulse widths within the measured range of 20 up to 200 ns. If the pulse widths were to be below 20 ns or in the sub-ns range, it is likely that the pulse width would play a more dominant role in the switching behaviors. However, due to the tester limitations used in this work, the write pulse width cannot be further reduced below 20 ns. Nevertheless, the MUX array demonstrates successful write operations without failures across a wide pulse width range down to 20 ns, coupled with appropriate bias voltages. Furthermore, the failure rates (red color) tend to slightly increase with decreasing the pulse width under the same bias voltage. The behaviors of write shmoo plots for −40 °C (Figs. 5(a) and 5(d)) and 125 °C (Figs. 5(c) and 5(f)) are basically the same as those of 25 °C, suggesting an excellent write capability for the MUX array across a broad temperature range.

Finally, we compare the 1 Kb MUX array with other published ones. Please note that there are very limited array-level data available for the SOT-MRAM worldwide so far^[37−39]. As summarized in Table 1, despite the larger CDs of the SOT-MTJs in our work due to process limitations compared to other work, we still achieved a high yield of 99.6% for the 1 Kb SOT-MRAM MUX array, with TMR ratios exceeding 80%, WER reaching a level of 10⁻⁶, which proves the good manufacturing process.

We demonstrated a 1 Kb SOT-MRAM MUX array with competitive performance compared with others as shown in Table 1. Moreover, we also showed sufficient write operation window without failures at a write pulse width of 20 ns or greater and above 1.2 V bias voltages, covering a wide temperature range from −40 to 125 °C. Following this first demonstration, we will focus on scaling down the MTJs’ CD and SOT channel lengths/widths to compete with other works^[32−40]. Based on the CD dependence of the switching current density observed in our study^[46], we would anticipate achieving sub-100 μA write current by reducing the MTJ CD to around 100 nm. We will also evaluate the array-level reliability, particularly the endurance performance. The SOT-MTJ CD/aspect ratio, SOT channel size and temperature dependence of the endurance will be systematically studied, which is not the scope of this paper and will be published elsewhere. This advancement would make SOT-MRAM highly promising as a replacement for slow SRAM in last-level cache applications.