[1] [1] RITHE R. The effect of random dopant fluctuations on logic timing at low voltage ［J］. IEEE Transactions on Very Large Scale Integration Systems, 2012, 20(5): 911-924.

[2] [2] KELLER S, HARRIS D M, MARTIN A J. A compact transregional model for digital CMOS circuits operating near threshold ［J］. IEEE Transactions on Very Large Scale Integration Systems, 2014, 22(10): 2041-2053.

[3] [3] FRUSTACI F, CORSONELLO P, PERRI S. Analytical delay model considering variability effects in subthreshold domain ［J］. IEEE Transactions on Circuits & Systems II: Express Briefs, 2012, 59(3): 168-172.

[4] [4] RITHE R, CHOU S, JIE G, et al. Cell library characterization at low voltage using non-linear operating point analysis of local variations ［C］// 2011 24th Internatioal Conference on VLSI Design. Chennai, India. 2011: 112-117.

[5] [5] RAMPRASATH S, VIJAYKUMAR M, VASUDEVAN V. A skew-normal canonical model for statistical static timing analysis ［J］. IEEE Transactions on Very Large Scale Integration Systems, 2016, 24(6): 2359-2368.

[6] [6] BALEF H, KAMAL M, KUSHA A, et al. All-region statistical model for delay variation based on log-skew-normal distribution ［J］. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2016, 35(9): 1503-1508.

[7] [7] DAS B P, AMRUTUR B, JAMADAGNI H S, et al. Voltage and temperature-aware SSTA using neural network delay model ［J］. 2011, 24(4): 533-544.

[8] [8] FISHMAN G. Monte Carlo: concepts, algorithms, and applications ［M］. Berlin: Springer, 1996.

[9] [9] BILBAO I, BILBAO J. Overfitting problem and the over-training in the era of data: particularly for artificial neural networks ［C］// 2017 Eighth International Conference on Intelligent Computing and Information Systems (ICICIS). Cairo, Egypt. 2017: 173-177.

[10] [10] HE R, HU B G, ZHENG W S, et al. Robust principal component analysis based on maximum correntropy criterion ［J］. IEEE Transactions on Image Processing, 2011, 20(6): 1485-1494.