Photonics Research, Volume. 11, Issue 7, 1275(2023)
High-efficiency reflector-less dual-level silicon photonic grating coupler
Fig. 1. (a) 2D schematic view and simulation layout of the proposed dual-level Si GC; (b) cross-sectional schematic with the parameter names used to indicate the GC dimensions.
Fig. 2. (a) 2D numerical simulations of the CE at 1550 nm as a function of the bottom linear apodization factor
Fig. 3. 2D numerical simulations of (a) directionality and (b) CE at 1550 nm as a function of the top linear apodization factor
Fig. 4. Fabrication process diagram for the dual-level GC: (a) starting from SOI wafer with a Si thickness of 340 nm; (b) bottom GC level etching; (c) top GC level etching; (d) waveguide etching; (e)
Fig. 5. Simulated (red curve) and experimentally measured (blue curve) CE as a function of wavelength for the fabricated dual-level GC with a bottom waveguide thickness
Fig. 6. (a) Peak CE (
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Valerio Vitali, Thalía Domínguez Bucio, Cosimo Lacava, Riccardo Marchetti, Lorenzo Mastronardi, Teerapat Rutirawut, Glenn Churchill, Joaquín Faneca, James C. Gates, Frederic Gardes, Periklis Petropoulos. High-efficiency reflector-less dual-level silicon photonic grating coupler[J]. Photonics Research, 2023, 11(7): 1275
Category: Silicon Photonics
Received: Mar. 1, 2023
Accepted: May. 6, 2023
Published Online: Jun. 25, 2023
The Author Email: Valerio Vitali (valerio.vitali@unipv.it)