AlGaN/GaN heterostructures exhibit a polarization-induced two-dimensional electron gas (2DEG) with high density and mobility, making them well-suited for meeting the increasing demands of intelligent power conversion systems and electric vehicles in terms of energy efficiency and power density^[1−7]. The utilization of complementary logic (CL) circuits based on GaN in driving and control circuits can further enhance the advantages offered by GaN power device^{[8, 9]}. By developing high-performance enhanced GaN p-FETs, it is possible to achieve CL in GaN, which can replace the commonly used GaN direct-coupled FET logic (DCFL), resulting in nearly zero static power consumption^{[10, 11]}. However, the development of p-channel GaN transistors, which play a pivotal role in GaN CL, remains challenging.

The limited hole mobility presents a significant challenge in achieving high performance for GaN p-FETs^[12−14]. Researchers have proposed various solutions to mitigate the issue of low I_D,MAX in GaN p-FETs. By integrating GaN p-FETs and NPN bipolars on a monolithic substrate, a maximum output current of 120 mA/mm is achieved^[15]. Through the utilization of superlattice, multiple-channel GaN p-FETs can achieve an increase in current, resulting in an I_D,MAX of 13 mA/mm^[16]. Compared to conventional top gate lateral structure devices, self-aligned components provide a viable approach for enhancing device performance by eliminating the access region^{[17, 18]}. The successful integration of FinFET and self-alignment technology in GaN p-FETs has led to a significant enhancement in I_D,MAX, demonstrating the achievement of GaN p-FETs with a current density of 300 mA/mm^[17]. The integration of self-alignment technology with p-channel GaN back gate injection transistors hold great promise in enhancing the performance of GaN p-FETs, leading to significant improvements in I_D,MAX, hysteresis, switching ratio, and sub-threshold swing (SS).

In this study, we employ the 2DEG situated at the AlGaN/GaN interface as a back gate to fabricate SA-BGITs^[19]. The utilization of the 2DEG back gate in SA-BGITs helps mitigate threshold voltage instability caused by interface states in the top metal−insulator−semiconductor (MIS) gate, resulting in a notable reduction in threshold hysteresis and SS. Moreover, SA-BGITs enable the enhancement of I_D,MAX through the modulation of conductivity via the injection of a significant number of electrons using the 2DEG back gate. This advancement in SA-BGIT technology paves the way for achieving high-performance GaN p-FETs and sets a solid foundation for the realization of high-performance GaN CL that seamlessly integrates into circuits.

The p⁺⁺-GaN/p-GaN/AlN (~2 nm)/AlGaN (~25 nm)/AlN (~1 nm)/GaN heterostructures were grown on Si substrates using metal organic chemical vapor deposition (MOCVD) technology^[20]. The SA-BGITs were fabricated on this heterostructure. The heterostructure features a heavily Mg-doped p⁺⁺-GaN layer, approximately 10 nm thick, overlaying a p-GaN layer with Mg doping levels of 4 × 10¹⁹−6 × 10¹⁹ cm⁻³ and a thickness of roughly 85 nm. It includes an approximately 2 nm thick AlN polarization-enhanced layer (AlN-PEL), an Al_0.25Ga_0.75N barrier layer about 25 nm thick, an unintentionally doped GaN layer, and an (Al)GaN buffer layer. The device structure and SEM images of SA-BGIT are illustrated in Fig. 1(a). The devices demonstrate Ohmic contacts, with a typical contact resistance (R_c) of 17.6 Ω·mm, a specific contact resistivity (ρ_c) of 1.05 × 10⁻⁴ Ω·cm², as illustrated in Fig. 1(c). Furthermore, the back gate also fabricates a robust Ohmic contact with the 2DEG, exhibiting a typical R_c of 0.98 Ω·mm, a specific contact resistivity (ρ_c) of 2.38 × 10⁻⁵ Ω·cm², as shown in Fig. 1(d).

Fig. 1(b) illustrates the manufacturing process of the device. N plasma injection was utilized for device isolation to prevent potential sidewall leakage that may result from mesa isolation. The p-type Ohmic contact was fabricated on the p⁺⁺-GaN layer as the source and drain by using lift-off. By utilizing a low power inductively coupled plasma (ICP) etching system, we achieved precise control over the etching duration and successfully fabricated gate trenches with a depth of 88 nm. Concurrently, we ensured the preservation of a slender 7 nm p-GaN layer within the channel region. Following this, we developed an automated stop-etching technique that utilizes Cl-based plasmas and was designed to eliminate residual p-GaN in the back gate electrode area. After an additional etching process in the area, the Ohmic metal was directly connected to the 2DEG using a Ti/Al/Ti/TiN, with the 2DEG serving as the back gate. Both the p-type Ohmic metal for the source/drain and the n-type Ohmic metal for the back gate were annealed under identical conditions, which involved exposure to air at a temperature of 550 °C for a duration of 1 min. Subsequently, the passivation process was carried out for both the trench region and the access area. The wafer underwent an in-situ remote plasma pre-treatment (RPP) within the PEALD system, followed by the growth of a 4 nm in-situ AlN in the same chamber^[21]. Afterwards, the samples were transferred to a plasma-enhanced CVD (PECVD) system for depositing a 20 nm SiN film on top of the PEALD-AlN layer^[22]. The gate width of the fabricated SA-BGITs is 100 μm.

The DC transfer characteristics of SA-BGITs (L_G = 3 μm) are shown in Fig. 2(a). When V_GS < −2.5 V, the transfer characteristics of SA-BGITs exhibit a secondary step, while I_G significantly increases. The increase in I_G results in an increase in I_S (I_S = I_D + I_G), which also leads to an increase in power consumption in CL (Fig. 2(b)). The increase in I_D is due to a large number of electrons injected through the back gate into the channel region, thereby generating holes to maintain charge neutrality (conductivity modulation)^[23]. The deep-level Mg doping results in shorter minority carrier (electrons) lifetimes, necessitating more injected electrons to form conductivity modulation, which also leads to gate leakage. Therefore, in future work, using u-GaN as the 2DHG channel layer is a feasible solution to extend electrons lifetimes and reduce gate leakage^{[24, 25]}. With reference to the power supply voltage of Si CMOS (1.2−1.8 V or even scaling down to less than 1.2 V), SA-BGITs can achieve a compromise between conductivity modulation and I_G at this voltage range. Due to the Ohmic contact established between the back gate and the 2DEG, there is less impact on controlling the 2DHG from any interface states related to the gate dielectric/p-GaN, resulting in an extremely low threshold hysteresis of 0.2 V and subthreshold swing of 173 mV/dec. The reason is that the back gate only has extremely low interface states or bulk traps^{[26, 27]}. However, during device ON-state operation, a small number of holes are trapped by the traps introduced by the etching at the PELAD-AlN/p-GaN interface, leading to negative threshold voltage drift^[28]. The device is similar to the TFT structure in terms of gate capacitance, where the additional area of the 2DEG has minimal impact on the gate capacitance and can be neglected^{[29, 30]}. However, the 2DEG back gate resistance will affect the switching speed of the device. The introduction of InAlN can increase the concentration of the 2DEG, thereby reducing the gate resistance in future work.

The DC output characteristics of SA-BGITs are depicted in Fig. 3(a). It is worth noting that SA-BGITs exhibit rapid I_D saturation when the V_GS bias is set to −4 V. The SA-BGITs demonstrate a larger maximum output current of 1.6 mA/mm and a R_on value of 548 Ω·mm. Furthermore, as depicted in Fig. 3(b), the reduction of L_G from 3 to 1 μm in SA-BGITs resulted in a significant increase in I_D,MAX, from 1.6 to 9.9 mA/mm. Table 1 benchmarks the fabricated SA-BGITs in this work with some other reported GaN p-FETs. SA-BGITs exhibit low threshold hysteresis, low SS, high I_D,MAX and high I_ON/I_OFF. The SA-BGITs back gate forms a p−i−n junction with the source/drain. When a negative bias is applied to the back gate, the p−i−n junction conducts forward, resulting in an increase in I_G, as is shown in Fig. 3(c). Future research could explore the introduction of AlInN or back gate Schottky contacts to suppress gate leakage current.

The characteristics of small-sized SA-BGITs suggest that scaling L_G can further improve the performance of SA-BGITs. The combination of this technique with top gate FinFET technology has the potential to achieve an outstanding switching ratio for the device. The utilization of this dual-gate device can significantly enhance the performance of GaN p-FETs^[29], thereby enabling GaN CL to potentially replace DCFL with its advantages of low power consumption, high frequency, and high integration.

The 2DEG at the AlGaN/GaN heterointerface offers another dimension to control over the p-channel positioned directly above it, resulting in the development of a novel structure of p-FETs known as SA-BGITs with a steep subthreshold swing of 174 mV/dec and a small threshold hysteresis of 0.2 V. The proposed SA-BGITs exhibit favorable scalability and conductivity modulation behavior with a I_D,MAX of 9.9 mA/mm (L_G = 1 μm), allowing for further enhancement of the current capability of GaN-based p-FETs. By incorporating these features, the challenges faced by GaN power IC can be effectively overcome, leading to significant advancements in both the design and performance of GaN CL.