Researching | An 80-GHz DCO utilizing improved SC ladder and promoted DCTL-based hybrid tuning banks

Journal of Semiconductors, Volume. 44, Issue 10, 102402(2023)

An 80-GHz DCO utilizing improved SC ladder and promoted DCTL-based hybrid tuning banks

Lu Tang^*, Yi Chen, and Kui Wang

Author Affiliations

Engineering Research Centre of RF-ICs & RF-systems, Ministry of Education, Southeast University, Nanjing 210096, China

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References(19)

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[3] C H Tsai, Z W Zong, F Pepe et al. Analysis of a 28-nm CMOS fast-lock Bang-Bang digital PLL with 220-fs RMS jitter for millimeter-wave communication. IEEE J Solid-State Circuits, 55, 1854(2020).

[4] C Zhang, Y X Xu, S J Ji et al. A design of DCO with 73.1% frequency tuning range based on switched transformer, 1(2021).

[5] F Yang, R H Wang, X Z Liu et al. A high frequency resolution digitally controlled oscillator with differential tapped inductor, 165(2015).

[6] Z Q Huang, H C Luong. A dithering-less 54.79-to-63.16GHz DCO with 4-Hz frequency resolution using an exponentially-scaling C-2C switched-capacitor ladder, C234(2015).

[7] Z Q Huang, H C Luong. An 82–107.6-GHz integer-N ADPLL employing a DCO with split transformer and dual-path switched-capacitor ladder and a clock-skew-sampling delta–sigma TDC. IEEE J Solid-State Circuits, 54, 358(2019).

[8] C Venerus, I. Galton. A TDC-Free Mostly-Digital FDC-PLL Frequency Synthesizer With a 2.8-3.5 GHz DCO. IEEE J Solid-State Circuits, 50, 45(2015).

[9] W H Wu, R B Staszewski, J R Long. A 56.4-to-63.4 GHz multi-rate all-digital fractional-N PLL for FMCW radar applications in 65 nm CMOS. IEEE J Solid-State Circuits, 49, 1081(2014).

[10] C M Lin, K Y Kao, K Y Lin. A wideband, low-noise, and high-resolution digitally-controlled oscillator for SDR applications, 270(2019).

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[13] F Ullah, Y Liu, X S Wang et al. Bandwidth-enhanced differential VCO and varactor-coupled quadrature VCO for mmWave applications. AEU Int J Electron Commun, 95, 59(2018).

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[16] T Y Lu, C Y Yu, W Z Chen et al. Wide tunning range 60 GHz VCO and 40 GHz DCO using single variable inductor. IEEE Trans Circuits Syst I Regul Pap, 60, 257(2013).

[17] S Yu, P R Kinget. Scaling LC oscillators in nanometer CMOS technologies to a smaller area but with constant performance. IEEE Trans Circuits Syst II Express Briefs, 56, 354(2009).

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[19] A Tarkeshdouz, A Mostajeran, S Mirabbasi et al. A 91-GHz fundamental VCO with 6.1% DC-to-RF efficiency and 4.5 dBm output power in 0.13-μm CMOS. IEEE Solid-State Circuits Lett, 1, 102(2018).

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Lu Tang, Yi Chen, Kui Wang. An 80-GHz DCO utilizing improved SC ladder and promoted DCTL-based hybrid tuning banks[J]. Journal of Semiconductors, 2023, 44(10): 102402

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Paper Information

Category: Articles

Received: Feb. 13, 2023

Accepted: --

Published Online: Dec. 26, 2023

The Author Email: Tang Lu (LTang)

DOI:10.1088/1674-4926/44/10/102402

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