Fig. 1. Block diagram of DPLL.

Fig. 2. (Color online) The architecture of the DCO with modified hybrid tuning banks.

Fig. 3. (Color online) The architecture of the FB.

Fig. 4. (Color online) Simulation results of the on-chip transformer. (a) Q-factor curve. (b) Coupling coefficient k curve.

Fig. 5. (Color online) Comparison of simulated results of the fine-tuning steps for the different fine-tuning banks.

Fig. 6. (Color online) The general layout of the promoted binary-weighted DCTLs in CB and MB.

Fig. 7. The model of promoted binary-weighted DCTLs.

Fig. 8. (Color online) (a) Comparison of the digital-controlled TLs for CB with promoted binary-weighted architecture and the conventional digital-controlled TLs for CB. (b) Simulated tuning characteristics of the DCO with the tuning banks based on the two kinds of digital-controlled TLs mentioned above. (c) Simulated L/bit of the two kinds of DCTLs for CB.

Fig. 9. (Color online) DCO chip microphotograph.

Fig. 10. Simplified schematic of phase noise measurement setup.

Fig. 11. (Color online) Measured medium-tuning characteristics.

Fig. 12. (Color online) Measured fine-tuning characteristics.

Fig. 13. (Color online) Measured DCO output spectrum.

Fig. 14. (Color online) Measured DCO phase noise at (a) 80.47 GHz and (b) 84.59 GHz.

Fig. 15. (Color online) Measured phase noise and FoM over the whole frequency tuning range of the DCO.