High-performance digitally controlled oscillators (DCOs) play a crucial role in the development of a credible digital phase-locked loop (DPLL)^[1−3]. However, the design of DCOs operating at higher frequency bands, especially in the millimeter wave band, remains challenging due to several limitations such as frequency resolution, tuning range and circuit complexity^{[4, 5]}.

As shown in Fig. 1, the DPLL is composed of time to digital converter (TDC), digital loop filter (DLF), a reference phase accumulator (RPA), a phase error calculation module and a variable phase accumulator (VPA). The RPA is responsible for counting the reference phase. The VPA is used to count an integral part of the CKV cycle after frequency division, and the TDC quantizes the fractional modulation. The phase error calculation module obtains the phase error, which arrives at the calibration module through the DLF. The calibration module then calculates a new OTW and sends it to the DCO. Since the fractional modulation is generated by the combination of other modules in the DPLL loop, the resolution of the DPLL loop can be further improved without putting additional fine- tuning pressure on the DCO. Optimization of the tuning bank structure is essential to balance the trade-off between better frequency resolution, lower phase noise, and higher operating frequency for a given millimeter-wave (mm-wave) DCO topology. A switched-capacitor (SC) ladder is often used to pursue higher frequency resolution with less chip size in contrast to the digitally controlled transmission lines (DCTLs)^[6−8]. The SC ladder with greater circuit complexity and parasitic capacitance is required for higher frequency resolution, resulting in a lower oscillation frequency and worse phase noise. In addition, the method of changing the operating frequency by controlling the inductance connected to the tuning bank through switches is used to achieve a higher frequency resolution. However, this also increases the complexity of the circuit and reduces the tuning range^{[9, 10]}. Another option is to use DCTLs in the tuning banks of the DCO to achieve a higher Q factor and lower substrate losses^{[11, 12]}. However, the parasitic capacitances caused by the large area of conventional DCTLs will also degrade the performance characteristics of the DCO, such as phase noise and oscillation frequency^[13]. Therefore, modifying the tuning banks of the mm-wave DCO to improve the trade-off between chip size, oscillation frequency, phase noise, and frequency resolution remains a challenge.

To address the above challenges, this paper presents an 80-GHz DCO based on modified hybrid tuning banks. An improved SC ladder based on the binary-weighted SC cell is used to realize the DCO trim group (FB), and the sub-MHz trim step size is obtained with low circuit complexity. In addition, the promoted binary-weighted DCTLs technology is adopted in the medium-tuning bank (MB) and coarse-tuning bank (CB) of the DCO to achieve lower phase noise and higher oscillation frequency with a smaller chip size. Measurement results indicate a reasonable compromise among higher oscillation frequency, more compact chip size, lower phase noise, and higher frequency resolution in the DCO.

As shown in Fig. 2, the tuning banks of the 80-GHz DCO consist of a fine-tuning bank based on an improved SC ladder coupled to the secondary coil of a transformer, a coarse-tuning bank, and a medium-tuning bank based on promoted binary-weighted DCTLs. Due to the optimized structure of the hybrid tuning resonator, only 16-bit binary control words are required to set the frequency of the DCO.

The SC-cell-based improved SC ladders proposed in this paper exhibits the advantage of lower circuit complexity. In addition, it helps to suppress the extra noise caused by more capacitive switches used in the conventional SC ladder. As shown in Fig. 3, the improved circuit topology is used in each SC unit stage of the SC ladder. An improved circuit topology replaces three thermometer-coded SC cells in a conventional circuit topology with two binary-weighted SC cells. The improved circuit topology allows eight modified SC ladder-based SC cells to achieve the same fine-tuning steps as twelve conventional SC ladder-based SC cells, while eliminating four switching tubes, reducing resonator tank losses and further optimizing the DCO's phase noise. The equivalent capacitance of the SC ladder shown in Fig. 3 can be expressed as^[14]

1Ceq≈C+(12+14+18+⋯+122n−1+122n)ΔC.

Here ΔC is the most negligible capacitance under the process of the SC ladder with n stage SC units. Eq. (1) shows that the minimum tunable capacitance can be reduced exponentially to 1/2²ⁿΔC. This also means that the fine-tuning steps of the DCO can be further improved. However, too many stages introduce problems, such as increased switch parasitic capacitance and excessive circuit complexity. Therefore, the FB of the DCO consists of four stages of SC units for a better trade-off.

To compensate for the reduced frequency resolution due to fewer SC unit stages to achieve sub-MHz fine-tuning steps, the improved SC ladder is attached to the secondary coil of the transformer with a lower coupling coefficient. Therefore, the larger capacitance change in the SC ladder can be converted into the smaller inductance change in the whole tuning resonator of the DCO by the secondary coil of the transforme^[15]. Fig. 4(a) shows that the Q of the two coils of the transformer at the operating frequency is greater than 15. Fig. 4(b) shows that the coupling coefficient of the transformer is less than 0.25, which meets the requirement of the weaker magnetic coupling between the two coils.

It can be seen from Fig. 5 that the simulated average fine-tuning step of the FB based on the improved SC ladder attached to the primary coil of the transformer is about 2 MHz. In comparison, that of the FB based on the improved SC ladder attached to the secondary coil of the transformer is 0.5 MHz.

The structure of the DCO's CB and MB is shown in Fig. 6. Compared with conventional thermometer-coded DCTLs, the number of coarse and medium control bits is reduced from 30 to 8 with the promoted binary-weighted DCTLs, and the total length is reduced by 34.3% (from 122.76 to 80.66 μm), which reduces fixed parasitic capacitance and passive component losses, making it more suitable for mm-wave DCOs.

The equivalent model for promoted binary-weighted DCTLs is shown in Fig. 7. L is the equivalent inductance every unit length of the DCTLs. C represents the coupling capacitance between two adjacent parallel DCTLs. C_M represents the MIM capacitance formed by the TLs and the metal strips underneath. Compared with conventional thermometer-coded DCTLs, this model can also realize the same frequency tuning range with a smaller chip size.

When C_M is turned on by the switches, the DCTLs' characteristic impedance can be calculated as

2Z0=L0/(C0+2nCM/2)(0⩽n⩽3).

From Eq. (2), it can be seen that more capacitance contributed by the closed switches can reduce the characteristic impedance of the DCTLs.

Figs. 8(a) and 8(b) show that the coarse bank based on promoted binary-weighted DCTLs can achieve the same frequency tuning range with a total length 31.7% (from 97.5 to 66.62 μm) shorter than that based on the conventional thermometer-coded DCTLs, and the control bits are reduced from 15 to 4, which reduces fixed parasitic capacitance and passive component losses. Likewise, the total length of the medium bank based on the promoted binary-weighted DCTLs is 44.4% (from 25.26 to 14.04 μm) shorter than the conventional thermometer-coded DCTLs and the control bits are reduced from 15 to 4. As a result, the proposed DCO can achieve a wider frequency tuning range and higher oscillation frequency with fewer control bits and a more compact chip size. Fig. 8(c) compares the length of each bit of the promoted and conventional DCTLs in the CB. The promoted binary-weighted DCTLs have the advantages of fewer switching circuit bits and smaller die sizes than conventional DCTLs. Therefore, the CB and MB of the DCO in this paper are implemented with the modified binary-weighted DCTLs.

As shown in Fig. 9, the DCO was fabricated in 40-nm CMOS. As shown in Fig. 10, the tuning word is fed into the chip's serial peripheral interface (SPI) module through a microcontroller. The SPI then converts the serial input to the parallel output, thus changing the tuning control words of DCO. The millimeter wave GSG probe is connected through the waveguide to the eighth harmonic mixer and finally to the FSUP50 spectrum analyzer.

The oscillation frequency range of the DCO is 79–85 GHz. Fig. 11 shows the measured medium-tuning curves under different coarse tuning codes. The average coarse-tuning step is about 380 MHz/bit, and the average medium-tuning step is about 33 MHz/bit. The measured fine-tuning characteristic is shown in Fig. 12. While both the control word of the MB and that of the C.B. are 0, the control word of the first four bits of the FB can achieve a frequency-tuning step of 2.8 MHz/bit, and the control word of the last four control bits of the FB can achieve a frequency-tuning step of 483 kHz/bit. This means that the tuning range of the fine-tuning bank is about 42 MHz. It is larger than the medium-tuning step of this frequency band. The tuning range of the medium-tuning bank is about 495 MHz, which is also larger than the coarse-tuning step of this frequency band. In total, the fine-tuning range can completely cover the medium-tuning bank step, and the medium-tuning range can also completely cover the coarse-tuning bank step.

Figs. 13 and 14 show the measured spectrum and phase noise, respectively. Fig. 15 shows the measured phase noise and FoM over the whole frequency tuning range of the DCO. When the oscillation frequency is 84.6 GHz, the phase noise is −114 dBc/Hz at a 10-MHz offset. The measured phase noise of the circuit was kept at a low level under the high noise level condition. It shows the circuit performance of good anti-noise ability and high reliability. The power dissipation of the core part of the DCO is about 16 mW from 0.9 V supply voltage. During the millimeter wave measurement, the eighth harmonic mixer, the millimeter-wave GSG probe, and the RF coaxial connecting line will all introduce insertion loss and reduce the power of the oscillation signal. Therefore, the measured output power of the millimeter wave DCO is –28 dBm.

Table 1 shows the performance comparison between the DCO implemented in this work and previous works. Excellent normalized figure of merit (FoM)^[16] and normalized figure of merit with area (FoM_A)^[17] are achieved considering the chip area.

An 80-GHz DCO with the modified hybrid tuning banks is investigated and fabricated in 40 nm CMOS for better tradeoffs among chip size, frequency resolution, oscillation frequency, and phase noise. The SC ladder based on the SC unit stages with improved circuit topology and the promoted binary-weighted DCTLs are incorporated into the tuning bank of the DCO. The oscillation frequency range of the DCO covers 79−85 GHz. The modified DCO exhibits an excellent FoM_A of −198 dBc/Hz compared to previous works. The DCO also achieves a high-frequency resolution of 483 kHz.