Fig. 1. The block diagram of chip

Fig. 2. The topology of the TIA module

Fig. 3. The effects of inductors on noise and bandwidth

Fig. 4. The effect of voltage protection topology

Fig. 5. The block diagram of AOC

Fig. 6. AOC accelerator topology and setup time

Fig. 7. Chip photo and package diagram

Fig. 8. Chip measurement setup

Fig. 9. Eye diagrams at different input optical power @10 Gbit/s

Fig. 10. Bit error rate curve@10 Gbit/s

Fig. 11. Eye diagrams at different input optical power @12.5 Gbit/s

Fig. 12. Bit error rate curve@12.5 Gbit/s

Fig. 13. Eye diagrams at different input optical power @2.5 Gbit/s

Fig. 14. Bit error rate curve@2.5 Gbit/s

Fig. 15. The setup time at different optical power