Fig. 1. (Color online) (a) Schematic cross-section of the p-well/deep n-well SPAD. (b) TCAD simulation of the reverse I−V characteristics.

Fig. 2. (Color online) TCAD simulation of the electric field for devices with guard ring width (a–c) GRW = 1, 2, 3 μm.

Fig. 3. (Color online) (a) TCAD simulation of electric field strength extracted at Y = 0.52 μm. (b) Drift path of minority electrons in the guard ring. (c) TCAD simulation of total current density extracted at Y = 0.52 μm.

Fig. 4. (Color online) Micrograph of SPADs with GRW = 1 and 2 μm fabricated in a 180 nm standard CMOS technology.

Fig. 5. (Color online) (a) Experimental setup for photon counting. (b) Measured reverse I−V characteristics of SPADs with two guard ring widths.

Fig. 6. (Color online) Variations of DCR (a) with V_ex at room temperature (T = 290 K) and (b) with the temperature at the excess bias of 2 V.

Fig. 7. (Color online) Measured PDP of SPADs at different excess bias voltages.

Fig. 8. (Color online) Measured AP of SPADs at different excess bias voltages.