Fig. 1. Schematic and implementation of hybrid integration of silicon photonic chip with InGaAs/InP SPAD array chip. (a) Cross-section view of the hybrid integration; (b) top view of the hybrid integration; (c) optical microscopic image of silicon photonic chip; (d) optical microscopic image of SPAD array chip; (e) process of flip-chip integration; (f) optical microscopic image of hybrid integration of silicon photonic chip with SPAD array chip

Fig. 2. Experimental setup for the hybrid integrated SPAD array's performance testing. (a) Setup for SPAD performance testing under 500 MHz sinusoidal gated quench circuit; (b) SPAD avalanche readout circuit

Fig. 3. Performance test results of SPAD₁ and SPAD₄ of the hybrid integrated SPAD array. (a) On-chip photon detection efficiency of SPAD₁ and SPAD₄; (b) dark count rate of SPAD₁ and SPAD₄; (c) after-pulse probability of SPAD₁ and SPAD₄; time jitter of (d) SPAD₁ and (e) SPAD₄ when bias voltage is 77.2 V

Fig. 4. HOM interference test setup of weak coherent states and experiment results. (a) Experimental setup for weak coherent HOM interference (only the on-chip components involved in the HOM interference are shown in the figure, while other unit components are omitted); (b) relationship between the coincidence count of two SPADs and delay