Journal of Semiconductors, Volume. 44, Issue 8, 082801(2023)

High threshold voltage enhancement-mode GaN p-FET with Si-rich LPCVD SiNx gate insulator for high hole mobility

Liyang Zhu1, Kuangli Chen1, Ying Ma2, Yong Cai2, Chunhua Zhou1、*, Zhaoji Li1, Bo Zhang1, and Qi Zhou1,3、**
Author Affiliations
  • 1State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China
  • 2Key Laboratory of Nanodevices and Applications, Suzhou Institute of Nano-tech and Nano-bionics, CAS, Suzhou 215123, China
  • 3Institute of Electronic and Information Engineering, University of Electronic Science and Technology of China, Dongguan 523808, China
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    Figures & Tables(11)
    (Color online) (a) Epitaxial structure and schematic of the proposed device. (b) The fabrication procedure. The I–V characteristic measured from TLM for the samples with (c) N-rich LPCVD SiNx and (d) Si-rich LPCVD SiNx.
    (Color online) The focused ion beam section of ~22 nm channel.
    (Color online) The transfer characteristic of (a) Si-rich sample and (b) N-rich sample. The output characteristic of (c) Si-rich sample and (d) N-rich.
    (Color online) The μeff and the nh of (a) Si-rich and (b) N-rich sample with ~48 nm trench.
    (Color online) (a) The focused ion beam section of ~12 nm channel. (b) The surface morphology characterized before/after recess.
    (Color online) The transfer characteristic of (a) Si-rich sample and (b) N-rich sample. The output characteristic of (c) Si-rich sample and (d) N-rich.
    (Color online) The ΔVTH with different VGS sweep ranges.
    (Color online) The Band diagram schematics of the MIS gate of Si-rich sample during the (a) initial state, (b) up sweep and (c) down back.
    (Color online) the Band diagram schematics of the MIS gate of N-rich sample during the (a) initial state, (b) up sweep and (c) down back.
    (Color online) The μeff and the nh of (a) Si-rich and (b) N-rich sample with ~58 nm trench.
    • Table 1. Benchmark of typical parameters of GaN p-FETs.

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      Table 1. Benchmark of typical parameters of GaN p-FETs.

      GroupMobility (cm2/(V∙s))ION/IOFFfVTH (V)ΔVTH (V@VGS_min)RON (kΩ∙mm)
      a mobility in channel; b mobility in access region;c defined at ID = 0.01 mA/mm; d defined by linear-extrapolation;e N. A. is abbreviation for “not available”; f IOFF in here was the current when VGS is biased to 0 V.
      This work19.4a5×105−2.3c−0.1 (@-10 V)5.7
      Xidian[14]2b~102−2.2dN. A.0.54
      Sheffield[16]11.8a~107−0.73c−0.12 (@−8 V)1
      HKUST[24]N. A.e~2×107−1.7c~−0.1 (@−6 V)0.65
      SINANO[22]11b~106−2.7c−2.4 (@−12 V)0.061
      MIT[12]15b~103.5dN. A.2.3
      MIT[13]11b~10−0.3dN. A.2.3
      MIT[18]10a~102−1N. A.2.4
      MIT[17]7.5a~1062N. A.
      HKUST[15]10.2b~2×107−1.7cN. A.
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    Liyang Zhu, Kuangli Chen, Ying Ma, Yong Cai, Chunhua Zhou, Zhaoji Li, Bo Zhang, Qi Zhou. High threshold voltage enhancement-mode GaN p-FET with Si-rich LPCVD SiNx gate insulator for high hole mobility[J]. Journal of Semiconductors, 2023, 44(8): 082801

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    Paper Information

    Category: Articles

    Received: Jan. 14, 2023

    Accepted: --

    Published Online: Sep. 21, 2023

    The Author Email: Zhou Chunhua (czhou@uestc.edu.cn), Zhou Qi (zhouqi@uestc.edu.cn)

    DOI:10.1088/1674-4926/44/8/082801

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