Chinese Physics B, Volume. 29, Issue 10, (2020)
Simulation study of device physics and design of GeOI TFET with PNN structure and buried layer for high performance
[1] G B Benneventi, E Gnani, A Gnud, S Reggianii, G Baccarani. IEEE Trans. Electron Dev., 62, 44(2015).
[2] , R Ranjan, K P Pradhan, L Artola, P K Sahu. Superlattices Micro., 97, 70(2016).
[3] N Damrongplasit, S H Kim, T K Liu. IEEE Electron Dev. Lett., 34, 184(2013).
[4] M Aslam, S Yadav, D Soni, D Sharma. Superlattices Micro., 112, 86(2017).
[5] H Y Kang, H Y Hu, B Wang. Chin. Phys. B, 25(2016).
[6] M Rahimian, M Fathipour. J. Comput. Electron., 15, 1297(2016).
[7]
[8] D Soni, D Sharma, S Yadav, M Aslam, N Sharma. Superlattices Micro., 113, 94(2018).
[9] C Alper, P Palestri, J L Padilla, M LonescuA. IEEE Trans. Electron Dev., 63, 2603(2016).
[10] Z Yang. IEEE Electron Dev. Lett., 37, 839(2016).
[11] W Wang, P F Wang, C M Zhang, X Lin, X Y Liu, Q Q Sun, P Zhou, D W Zhang. IEEE Trans. Electron Dev., 61, 193(2014).
[12] W Li, H Liu, S Wang, S Chen. IEEE Electron Dev. Lett., 38, 403(2017).
[13] S Chen, H Liu, S Wang, W Li, X Wang, L Zhao. Nanoscale Research Lett., 13, 313(2018).
[14] R M Imenabadi, M Saremi, W G Vandenberghe. IEEE Trans. Electron Dev., 64, 4752(2017).
[15] B Singh, T Rai, D Gola, K Singh, E Goel, S Kumar, P Tiwari, S Jit. Materials Science in Semiconductor Processing, 71, 161(2017).
[16] K Low, C Zhan, G Han, Y Yang, K Goh, P Guo, E Toh, Y Yeo. Jpn. J. Appl. Phys., 51, 02(2012).
[17] S Mitra, R Goswami, B Bhowmick. Superlattices Micro., 92, 37(2016).
[18] P Y Wang, B Y Tsui. IEEE Trans. Electron Dev., 63, 1788(2016).
[19] H Wang, G Han, X Jiang, Y Liu, J Zhang, Y Hao. IEEE Trans. Electron Dev., 66, 1985(2019).
[20] T Han, H Liu, S Chen, S Wang, W Li. Micromachines, 10, 424(2019).
[21] U Avci, B Chu-Kung, A Agrawal, G Dewey, V Le, 891(2015).
[22] T Krishnamohan, D Kim, S Raghunathan, K Saraswat(2008).
[23] Q Zhang, S Sutar, T Kosel, A Seabaugh. Solid-State Electrons, 53, 30(2009).
[24] S Takagi, W Kim, K Jo, R Matsumura, R Takaguchi, T Katoh, T Bae, K Kato, M Takenaka. ECS Trans., 86, 75(2018).
[25] T Katoh, R Matsumura, R Takaguchi, M Takenaka, S Takagi. Jpn. J. Appl. Phys., 57, 04(2018).
[26] R Matsumura, T Katoh, R Takaguchi, M Takenaka, S Takagi. Jpn. J. Appl. Phys., 57, 04(2018).
[27] X Liu, H Y Hu, B Wang, M Wang, G Han, S Cui, H M Zhang. Superlattices Micro., 102, 7(2017).
[28] B Wang, H M Zhang, H Y Hu, X W Shi. Chin. Phys. B, 27(2018).
[29] J P Colinge, C W Lee, A Afzalian, N Akhavan, R Yan, I Ferain, P Razavi, B O’Neil, A Blake, M White, A Kelleher, B McCarthy, R Murphy. Nat. Nanotechnol., 5, 225(2010).
Get Citation
Copy Citation Text
Bin Wang, Sheng Hu, Yue Feng, Peng Li, Hui-Yong Hu, Bin Shu. Simulation study of device physics and design of GeOI TFET with PNN structure and buried layer for high performance[J]. Chinese Physics B, 2020, 29(10):
Received: Apr. 23, 2020
Accepted: --
Published Online: Apr. 21, 2021
The Author Email: Wang Bin (wbin@xidian.edu.cn)