Fig. 1. (Color online) Comparison of reference voltage and control logic schemes (a) synchronous logic with on-chip V_REF; (b) synchronous logic with off-chip V_REF; (c) timing of asynchronous logic; (d) timing of proposed HYSAS logic.

Fig. 2. (Color online) Proposed HYSAS SAR control logic for a N-bit SAR ADC.

Fig. 3. (Color online) The mathematical expectation of the conversion time for each bit of the SAR with asynchronous control logic.

Fig. 4. (Color online) Simulated waveforms of V_REF and differential V_DAC for a 16-bit 18-MSPS SAR ADC model.

Fig. 5. (Color online) Simulated SFDR and SNDR of ADC models with various control logic schemes considering the V_REF’s ringing due to bonding inductance.

Fig. 6. (Color online) Architecture and timing of 16-bit, 18-MSPS SAR ADC with proposed HYSAS control logic.

Fig. 7. (Color online) Schematic and timing of the low-voltage (1.2 V) auto-zero comparator with a 2-stage preamplifier.

Fig. 8. (Color online) Structure of the off-chip LMS calibration with FIR-based signal extraction.

Fig. 9. (Color online) Die photo.

Fig. 10. (Color online) Power consumption breakdown.

Fig. 11. (Color online) ADC test-board and calibration FPGA (ZYNQ-7000).

Fig. 12. (Color online) Measured spectrum for a 2.88-MHz input frequency with (a) FIR-based LMS and (b) fitting-based LMS scheme.

Fig. 13. (Color online) Measured SNDR/SFDR for 100-kHz input frequency under different sampling rates.

Fig. 14. Measured INL and DNL for 16-bit resolution after calibration.