With the fast development of emerging applications in past decades, such as internet of things (IoT), medical devices, and wireless communications, there has been an increasing demand for analog-to-digital converters (ADCs) with higher performance metrics in terms of precision and speed. Among various ADC architectures, successive-approximation-register (SAR) ADCs have attracted much research interest. The sample rate (f_s) and resolution (N) of SAR ADCs have increased steadily because their digital-like structure can benefit fully from the advanced process to achieve high precision with low power consumption and compact size^[1−3].

A multitude of mature SAR ADCs with high sampling rates (≥10 MSPS) and moderate resolutions (6−12 bits) have been developed for either academic or industrial purposes^[4−8]. Among them, the time-interleaved SAR ADCs with multiple sub-ADC channels can achieve a sampling rate up to several GSPS^[9], whereas the timing skew, gain, and offset mismatches between the sub-ADCs deteriorate the ADC’s spurious-free dynamic range (SFDR) remarkably, necessitating complex calibration circuits with considerable hardware and power consumption overhead^[10]. Therefore, research efforts have been made to improve the conversion rate of the single-channel ADC, resulting in many effective circuit techniques, such as multi-bit quantization per cycle^{[11, 12]}, alternate use of comparators^[13], and direct control of multi-bit capacitor arrays by multiple comparators^[14]. These strategies significantly reduce the conversion time for each bit, leading to remarkable advancements in SAR ADC’s sampling rate.

On the other hand, improving the resolution of the SAR ADC (e.g. to 13−16 bits) while maintaining the sampling rate over 10 MSPS also involves hard design challenges^[14−19]. The single-channel SAR ADC in Ref. [16] achieves 16-bit resolution with a sampling rate of 16 MSPS using a 40-nm CMOS process while consuming 16.3-mW power consumption. This achievement showcased the SAR ADC’s excellent compatibility with advanced processes and low-power supply voltages. However, it is difficult to improve the sampling rate and resolution simultaneously further with acceptable power efficiency. For a SAR ADC with an accuracy of N bits, as the sampling rate increases, the conversion time for each bit (<1/(N·f_s)) decreases rapidly, while the bit-by-bit reference recovery time also reduces. As a result, the sample-by-sample error becomes more pronounced^[20]. Moreover, with the precision improved, the comparator noise and offset need to be suppressed significantly. The introduction of the floating inverter amplifier (FIA) enables lower comparator noise performance with reduced consumption^[21], whereas the FIA’s performance is prone to process, voltage, and temperature (PVT) variations. The idea of kT/C noise cancellation allows for sampling with relatively small capacitance, thereby improving the energy efficiency of the ADC^{[17, 22]}. However, extra amplifiers are required to support the function of the kT/C noise cancellation. The technique of repeating the comparison for the least significant bit (LSB) relaxes the requirements for comparator noise performance, at the price of lowering the overall conversion speed^[23]. In addition, the circuit and power consumption overhead caused by the input buffer also need to be addressed for a high-speed precision SAR ADC^{[15, 24]}. Therefore, it is still urgent to investigate new SAR ADC circuit structures that can achieve high speed and high resolution with low overhead for circuit and power consumption.

In this paper, the main effort is made to realize a more reasonable allocation scheme of the CDAC switching time (T_sw) and the comparator regeneration time (T_comp), providing more settling time without imposing demands for higher comparison speed. The idea is achieved by the proposed hybrid synchronous and asynchronous (HYSAS) logic based on a delay-locked loop (DLL), which provides longer CDAC settling time than the existing synchronous and asynchronous SAR ADCs. Therefore, the issue of incomplete settling or ringing in the DAC reference voltage (V_DAC) can be solved to a large extent. Based on the HYSAS logic, a 16-bit, 18-MSPS flash-assisted SAR ADC is implemented with 40-nm CMOS technology, achieving 75.98-dB signal-to-noise-and-distortion ratio (SNDR) and 94.02-dB SFDR with 10-mW power consumption.

This paper is organized as follows. Section 2 explains the basic principles of the HYSAS SAR Control logic, while Section 3 provides details of the ADC circuit structure. The measurement results are presented in Section 4 followed by the conclusion drawn in Section 5.

Usually, the reference voltage (V_REF) for a SAR ADC can be generated by an on-chip reference circuit or provided by a separate reference chip. The schemes of on-chip V_REF can avoid the ringing in V_DAC induced by the bonding wire inductance at the V_REF pad. Fig. 1(a) shows a conceptual example of N-bit top-plate-sampling SAR ADC with on-chip V_REF, in which the V_REF includes an unavoidable noise source v_n. The driving capability of V_REF is modeled by the source resistance, R_S. To suppress v_n, an on-chip bypass capacitor, C_BP, is usually needed. However, limited by chip area, C_BP is usually in the pF order and can hardly exceed several nF. Therefore, the on-chip V_REF scheme usually shows relatively large noise contribution from V_REF.

On the other hand, the scheme of off-chip V_REF can use a large C_BP (up to several μF) to significantly suppress the v_n from V_REF, as shown in Fig. 1(b). However, the bonding wire inductance (L_bond) for V_REF forms an LC resonant network with the parasitic C_pad and the CDAC. Therefore, when the CDAC switches, remarkable ringing will appear at the V_REF terminal and pass to V_DAC, leading to possible conversion error. Although the on-chip reference solution can circumvent the problem of reference ringing caused by package parasitic inductance, it still suffers from the issue of insufficient settling of V_REF because of the relatively high impedance of the on-chip reference voltage source. It should be noted that the inductance connected to the input terminal (V_in) shows much less influence, because the sampling time is usually much longer than T_sw.

Figs. 1(a) and 1(b) also show the simplified timing for synchronous logic with off-chip and on-chip V_REF, respectively. As can be seen, after the CDAC samples V_in when ck_s is high, the comparator operates at the falling edge of ck_c to solve the MSB in the first T_comp interval. Then, the MSB capacitor (2^N−1C_u) switches from V_CM to V_REF or ground according to the comparison results. Due to the limited driving capability of V_REF (Fig. 1(a)) or the inductor-induced ringing (Fig. 1(b)), V_DAC may not settle to its final value in the T_sw interval, leading to mistakes in decision of the next bit. Although a CDAC with redundancy can help to recover the settling error, high-speed SAR ADCs often insert 2−3 extra redundancy bits providing only a small redundancy range. In addition, the ringing and incomplete settling of V_DAC are input-dependent, which may deteriorate the SFDR.

For an asynchronous SAR ADC, the simplified conceptual timing diagram is shown in Fig. 1(c), in which the end of the sampling phase triggers the comparison for the MSB. Once the comparator completes latching, it generates a rising edge for signal VALID, which then starts the T_sw interval immediately. Without a synchronous clock, T_sw is usually generated by an open-loop delay cell, which may fluctuate remarkably due to PVT variations. Moreover, although the adaptive T_comp allows using longer T_sw, a moderate nominal T_sw value is often insufficient for the most significant bits (MSB) but overdesigned for the least significant bits (LSB).

In order to improve the sampling rate of the SAR ADC while avoiding the drawbacks of asynchronous logic that is susceptible to process, voltage, and temperature (PVT) variations, this paper proposes a hybrid synchronous and asynchronous (HYSAS) control logic, with circuit structure shown in Fig. 2. The timing diagram of the HYSAS scheme, depicted in Fig. 1(d), maintains the reliable and concise design features of synchronous logic, while incorporating the advantages of adaptive comparison time from asynchronous schemes. As a result, longer T_sw is realized for V_DAC settling and a more rational time allocation strategy can be employed.

An advantage of the HYSAS logic lies in that it requires only a few logic gates, thus only introducing a negligible excessive delay in the critical path. The added control logic block is referred to as the hybrid logic unit (HLU). Similar to the asynchronous logic, the signal that enables the comparator (rising edge at port A of the HLU) also enables the operation of the DFF (data flip-flop) in the HLU concurrently. When the comparator has obtained the comparison result (the signal VALID switches to a high state), the CDAC starts switching accordingly. Unlike the asynchronous logic, in the event that the comparator’s metastability or other errors cause the signal VALID not to toggle within the expected time, the synchronous clock (rising edge at port B of the HLU) terminates the current comparison and initiates the switching phase of the CDAC. Controlled by the designed timing, the dynamic latch output (V_comp) resets to logic low earlier than the rising edge of the HLU output, ensuring clear switching of the CDAC. The delay module in the HLU is employed to prevent the VALID signal of the previous comparison from influencing the subsequent bit.

Intuitively, compared to the synchronous logic, the HYSAS scheme can adaptively allocate comparation time per bit, thereby providing longer switching time for the CDAC than the synchronous logic. On the other hand, the HYSAS scheme can forcefully interrupt the prolonged comparison phase due to metastability or other nonideal factors, thereby providing more settling time for the CDAC’s switching compared to the asynchronous logic in these cases. The related error caused by metastability can be recovered by a proper redundancy range. Therefore, while the probability of metastability occurrence in HYSAS is similar to synchronous logic^{[25, 26]} (depending on the proportion of T_comp), the resulted error is smaller than that of the asynchronous logic^[27] even in the presence of metastability. To verify the effectiveness of the HYSAS logic, theoretical analysis and verification with behavioral modeling are given below.

Before demonstrating the improved allocation of the settling time, several key parameters are defined at first, which are crucial for the following derivations. We consider a pure asynchronous SAR ADC with B bits excluding redundancy, where the input range is V_FS, and the power supply voltage is V_DD. Considering the operation of the comparator, the decision is referred to as a 'hard decision' if the differential voltage on the DAC is less than LSB/2; otherwise, it is termed as an 'easy decision'. A uniform distribution is assumed for the input signal. Furthermore, a comparator regeneration time constant of τ₁ is assumed, with the impact of the pre-amplifier being neglected. Following the classical synthesizable design approach, the switch array scales proportionally with the capacitor array, therefore, each bit has the same switching time constant of τ₂. To illustrate that the HYSAS can realize more rational time allocation between comparison (T_comp) and CDAC switching (T_sw) than the asynchronous logic, we attempt to prove that the time expectation required for each bit is almost constant in the SAR process for the asynchronous logic.

For the decision of the i-th bit in a B-bit SAR ADC with asynchronous logic, the mathematical expectation of the easy decision time can be derived as^[26]

1teasy,iτ1=1VFS/2i−1[∫−VFS/2i−VFS/2B+1ln(−VDDx)dx+∫−VFS/2i−VFS/2B+1ln(VDDx)dx]=1−2i−B−1+[i−(B+1)2i−B−1]ln(2)+(1−2i−B−1)ln(VDDVFS).

Assuming V_DD = V_FS, the above equation can be simplified to

2teasy,i/τ1=1−2i−B−1+[i−(B+1)2i−B−1]ln(2).

Similarly, the mathematical expectation of the hard decision time is

3thard,iτ1=1VFS/2i−1(∫−VFS/2B+10ln(−VDDx)dx+∫0−VFS/2B+1ln(VDDx)dx)=2i−B−1[(B+1)ln(2)+1].

The minimum of the mathematical expectation of the switching time, t_sw,i, for the i-th bit can be obtained as

4VFS2ie−tsw,iτ2VFS2B+1⇒tsw,i/τ2(B+1−i)ln(2).

The switching time constant, τ₂, and the comparator regeneration time constant, τ₁, are usually of the same order of magnitude in the SAR ADC. For a pure asynchronous SAR ADC with B = 16, the total time for each bit can be obtained as the sum of t_easy,i, t_hard,i, and t_sw,i, as shown in Fig. 3, in which we assume τ₁ = τ₂ = τ for simplicity.

It can be observed that the time expectation required for each bit of the asynchronous SAR ADC is approximately constant. Therefore, extensive time waste would occur in cases where the occurrence of easy decision is much higher than the occurrence of hard decision in an entire conversion process. On the other hand, the CDAC switching time is fixed for the asynchronous logic, whereas the practical requirement minimum T_sw for the MSBs is much higher than that for the LSBs. This means that the time allocation of the asynchronous logic faces hard tradeoffs.

On the contrary, the proposed HYSAS scheme combining the synchronous and asynchronous control logic can lead to a more rational time allocation of the SAR process. Although it allocates equal time for each bit like that in the synchronous logic, the merit of adaptive comparison ensures better usage of the clock period to perform comparison and CDAC switching. For the MSBs, as easy decision is more likely to happen (which means that T_comp can be much shorter), the HYSAS logic ensures the required longer time for CDAC switching. On the other hand, as prolonged comparison phase due to metastability can be stopped by the HYSAS logic, the loss in the signal-to-metastability error ratio (SMR) caused by hard decisions can also be alleviated with proper redundancy range offered by the CDAC.

To efficiently validate theoretical analysis and focus on the phenomenon rather than circuit details, we establish a behavioral MATLAB model for a 16-bit, 18-MSPS SAR ADC with different control logics and off-chip V_REF (1.6 V) considering non-ideal factors such as redundancy, parasitic inductance, and pre-amplifier effects. Based on the commonly used SAR ADC model, the effect of reference voltage ringing due to bonding-wire inductance is further added. For a classical behavioral-level SAR ADC model with ideal reference voltage, the voltage waveform at the bottom plate of related DAC capacitor exhibits a first-order RC step response in each switching step. Considering the impact of bonding wire parasitic inductance, a second-order RLC step approximation can be used with C_BP >> C_CDAC + C_PAD. This modeling method can be applied in the SAR ADC with various control logic to simulate the effect of reference voltage ringing, in which the residue voltage’s change on the top-plate of the CDAC can be solved according to the criterion of charge conservation. In the case of synchronous logic, the DAC residue voltage waveform is calculated using a fixed T_sw = T_step/2. For the asynchronous logic, the comparison duration, T_comp, is the sum of the latch’s regeneration time dependent on the residue of the previous step and the logic delay, while the CDAC switching is also a fixed value. For the HYSAS scheme, T_comp is calculated like that for the asynchronous logic, whereas T_sw for calculating the DAC voltage waveform is an adaptive value of T_step − T_comp when T_comp < T_step/2. Otherwise, the comparison is forced to complete and T_sw = T_step/2 is used to calculate the DAC voltage waveform. It is noteworthy that the peak amplitude of DAC voltage ringing is positively related to the switching energy. Therefore, this design adopts a Vcm-based switching scheme with low switching energy^[28]. Typical circuit parameters are adopted as L_bond = 2 nH with 200 mΩ series resistance, C_PAD = 1 pF with 100 Ω substrate resistance in series, C_{CDAC, tot} = 6.144 pF. The on-resistance of the switches is also included in the model. Fig. 4 plots the simulated V_REF and differential V_DAC waveforms in a typical conversion process with the synchronous logic, showing serious ringing in the two voltages. Although the ringing decays along the conversion process, it is still near 100 μV at the last two steps, which is much larger than the LSB of a 16-bit ADC. Fig. 5 illustrates a comparison of simulated SNDR and SFDR for various control logics. The results indicate that the three schemes (synchronous, asynchronous, and HYSAS) exhibit the same optimal performance for f_s up to 16-MSPS, as the V_DAC settles effectively within the time T_sw for all three cases. Nevertheless, when the sampling frequency reaches 18 MSPS, only the proposed HYSAS SAR logic exhibits a marginal decline in performance. In contrast, the SNDR and SFDR of the other two schemes decrease by approximately 10 dB due to V_REF ringing and other factors. Due to the modeling inaccuracy of the parasitic inductance caused by the bonding wire and significant variations between different batches in fabrication, the simulations presented above serve merely as guidance for the design.

Fig. 6. shows the architecture of the 16-bit, 18-MSPS SAR ADC with the proposed HYSAS control scheme and off-chip V_REF. The core circuit consists of an auxiliary flash ADC, a 16-bit segmented CDAC with three extra redundant bits, a comparator with pre-amplifier, the HYSAS SAR logic. The flash-SAR hybrid structure can reduce the overall conversion time while decreasing the swing of the DAC voltages, thereby accelerating the conversion process and consequently improving the design's power efficiency. To achieve a sampling rate of 18 MSPS, a 3-bit resolution is chosen for the flash ADC considering the tradeoff between speed and power consumption. In order to generate a robust clock network that can scale automatically with the sampling frequency in the reasonable frequency range, this design adopts a DLL-based clock scheme, which generates a 48-phase clock bus for the synchronous clock (ck_sync) generator from the main input clock signal, ck_main. Unlike the conceptual mode in Fig. 1, the presented ADC adopts bottom-plate sampling structure to avoid coupling of the input signal through the opened sampling switch in the conversion process. In addition, bootstrapping is applied for the sampling switches to ensure high linearity. To provide large signal range while ensuring high-speed operation, the comparator and logic circuits are designed with 40-nm core transistors powered by 1.2 V, while the CDAC switches and the flash ADC are designed with I/O transistors powered by 1.8 V.

The segmented CDAC array with detailed capacitance ratio is also shown in Fig. 6, which adopts custom-designed MOM (metal-oxide-metal) capacitors with C_u = 24 fF. Three redundant capacitors are included in the three segments, respectively, which can provide about 6.5% redundance range to recover a small portion of decision errors caused by incomplete settling of the V_DAC. The CDAC array employs a V_CM-based scheme to minimize power consumption during reference switching, thereby reducing V_DAC ringing. Only the high-segment capacitors (C₁₀−C₁₆ and C_d1) are utilized for sampling the input signal. To circumvent the need for a precise and high-speed common-mode voltage generation circuit, this design incorporates a split-CDAC structure that splits the CDAC array into two equal parts to perform binary switching^[19]. With sampling capacitance of 6.144 pF, the SNR considering only the kT/C noise can fulfill the requirement of the 16-bit ADC with a 1.6-V V_REF.

Similar to that in Ref. [16], the auxiliary 3-bit flash ADC performs a fast and coarse quantization to solve the 3 MSBs. With the 3 MSBs results from the flash ADC, the CDAC switching for the 3 MSBs can be performed simultaneously without performing the SAR process, which not only allows for longer switching time to accommodate the large V_DAC ringing in the following switching steps, but also can save overall conversion time as less SAR steps are needed. Due to the redundancy of the SAR DAC, an error within 1 LSB of the flash sub-ADC can be compensated by the CDAC. The simulation results demonstrate that the inclusion of redundant capacitance (C₁₄ = 16C_u) following the MSB-3 capacitance (C₁₅ = 16C_u) effectively compensates for errors introduced by the mismatch between the auxiliary ADC and the main ADC.

To mitigate the impact of input-referred random offset and noise of the dynamic pre-amplifier and latch, the comparator adopts a structure comprising a two-stage static pre-amplifier followed by a latch for the quantization operation, as illustrated in Fig. 7 with the corresponding schematic and timing. The residual voltage generated by the CDAC is amplified by the pre-amplifier and fed to the latch to make a decision. In the first stage of the pre-amplifier, a cross-coupled MOS pair is utilized to enhance the gain through weak positive feedback. During the sampling phase, the pre-amplifier undergoes auto-zero operation to eliminate the offset and reduce 1/f noise. Additionally, both stages are designed with a folded input structure to facilitate low-voltage operation. The latch circuit employs two pairs of cross-coupled positive feedback transistors to enhance the sensitivity and regeneration speed. During the interval of CDAC switching, both the preamplifier and latch are reset to the common-mode voltage to prevent memory effects from affecting the subsequent comparisons. Simulations including PVT variations show that the comparator noise is less than 80 μV∙rms. According to the derivation in Ref. [29], the noise performance of the comparator meets the requirement of this design.

The simplified timing allocation for the ADC is also given in Fig. 6. As shown, with the DLL-based clock scheme, one period of the sampling clock is divided into 48 equal slots with time of Δt. To ensure high linearity, the sampling duration is 10Δt. After that, the flash ADC uses only 1Δt to solve the 3 MSBs, and the following 2Δt is used to perform CDAC switching. Then, the HYSAS logic works to complete the conversion of the following 13 bits in 26Δt. It should be noted that, in the practical conversion process, the T_comp is the overall time for pre-amplifying and latching. For the last 3 bits, as the residue is quite small and can be corrupted by the reference ringing induced by the bond wire inductance, the duration of each step is allocated by 3Δt to permit a longer time for T_comp. Simultaneously, a longer bit cycle can effectively lower the probability of metastability, thereby enhancing both dynamic and static performances.

It is known that the capacitor mismatches in the CDAC cause a hard limit to the achievable accuracy (<12 bits) of the SAR ADC without calibration. Many calibration methods for the CDAC mismatch have emerged in the past years, such as the algorithms of dynamic element matching (DEM)^[30], dynamic weighted averaging (DWA)^[31], and mismatch error shaping (MES)^[32] used in the noise-shaping SAR ADCs, which necessitates oversampling to allow the operation for noise shaping, resulting in complex circuits and reduced conversion speed. The calibration methods adopted in Refs. [33] and [34] use two split-ADCs or an additional low-speed precision ADC to extract the CDAC weights in the background, which may lead to extra digital power consumption for the calibration circuits.

Since the CDAC mismatch is mainly susceptible to process variations, foreground calibration of CDAC weights is usually sufficient. This paper presents an LMS-based foreground calibration algorithm implemented with an off-chip FPGA, as illustrated in Fig. 8. With a sinusoidal input as the reference signal for the calibration algorithm, this work uses an N-tap bandpass finite-impulse-response (FIR) filter to generate the expected reference signal from the ADC output. The delay unit (delay by N/2) is included to match the phase shift between the input digital code and the filtered expected signal. The presented calibration scheme differs from the classical four-parameter curve-fitting based LMS calibration^[35] only in the way of generating the expected reference sinusoid signal. Thus, under the condition of an ideal input sinusoid signal for calibration, both approaches would exhibit similar convergence speed and accuracy. However, for the calibration of high-precision (>16 bits) SAR ADCs, the curve-fitting method may cause mismatch between the reference sinusoid signal generated by curve fitting and the real input signal when the input sinusoid signal contains some non-idealities caused by either the signal source or the on-board signal driver. Such mismatch can cause inaccurate weight estimation with the LMS method. In contrast, adopting the proposed bandpass FIR filtering approach to extract the reference signal can retain the possible in-band non-idealities of the real input signal to some extent, thereby improving the accuracy of weight estimation while reducing the requirements for the input reference source for calibration (including the front-end buffer).

Hardware synthesis of the calibration algorithm is performed using Xilinx's Vivado tool with a ZYNQ-7000 FPGA as the template. Due to the relatively slow convergence speed of high-order FIR filter, the calibration algorithm can converge within about 1000 ADC data points (about 100 μs for a 10-MHz calibration clock frequency), including reference signal extraction and LMS-based capacitor weights estimation. The weight correction module within the green shaded box in Fig. 8 incurs a hardware overhead of about 600 look-up tables (LUTs) and 300 flip-flops (FFs), which can be implemented on-chip with small area overhead and negligible power consumption. All other circuit blocks of the calibration scheme can be implemented in the FPGA-based hardware setup of the test environment. Therefore, the presented scheme can support a fully hardware-based calibration and test scheme for mass production, without sending the ADC data to a PC-based software for calculation and calibration. The overall time needed for calibration can be shorter than the software-based fitting method. Therefore, the proposed method permits a low-cost calibration and test scheme.

The 16-bit, 18-MSPS prototype ADC is fabricated using a standard 40-nm CMOS process and occupies an active area of 0.1 mm², as shown in Fig. 9. The 1.6-V reference voltage is externally derived through resistor voltage division based on an off-chip (ADR4525). The chip's total power consumption is 10 mW, including the contributions from the DLL, flash sub-ADC, CDAC, bootstrap switches, comparator, digital logic, and other circuits (bias circuits, common-mode level generation circuits, level shifting, and other related circuits), as the power consumption breakdown shown in Fig. 10. The comparator’s power consumption includes the contribution from the preamplifier and the latch.

The measurement setup includes a main PCB and an FPGA (ZYNQ-7000), as shown in Fig. 11. The main PCB is used to mount the presented ADC chip, and other necessary chips and devices, while the FPGA is used to acquire the ADC’s output for further process. On the PCB, the input signal driver is implemented by a separate fully differential operational amplifier chip (ADA4932-1), and an RC low-pass filter network is placed between the driver and ADC for anti-aliasing filtering. The external reference clock is provided by the SMA100B, while the input signal is generated by a signal source and further processed by an off-chip bandpass filter. Figs. 12(a) and 12(b) plot the measured output spectra of the ADC for a 2.88-MHz, 0-dBFS input signal after calibration with the software-based curve-fitting calibration method and the presented hardware-based FIR calibration method, respectively. As is shown, the ADC achieves a 75.98-dB SNDR and a 94.02-dB SFDR after calibration with the presented method, which is improved about 0.7 dB compared to the results from the conventional curve-fitting method. The results verify the effectiveness of the presented hardware-based calibration method. The remained 2^nd and 3^rd-order harmonics in the spectrum after calibration are mainly limited by the nonlinearity of the off-chip input buffer. As shown in Fig. 13, the ADC maintains an SNDR greater than 75 dB and SFDR greater than 90 dB when the sampling frequency f_s varies from 1 to 20 MHz. At a sampling rate under 5 MSPS, the achieved SNDR and SFDR are even over 81 and 95 dB, respectively. The degradation of the dynamic performance at high f_s is mainly caused by the insufficient driving capability of the input buffer. The static performance is also measured at 16-bit resolution using a high-precision ramp signal input, with the results depicted in Fig. 14. The measured INL and DNL are −1.27−2.11-LSB and −0.84−0.93-LSB, respectively.

Table 1 summarizes the performance of the proposed ADC with comparison to other recently reported high-speed, high-resolution SAR ADCs. As shown, the achieved Schreier figure of merit (FoM_S) is better than all the ADC except for that in Ref. [36]. From the aspect of the effective noise under a given reference voltage, the specification of effective total noise is defined and compared in Table 1. As is shown, the ADC in this paper achieves the lowest equivalent total noise at the smallest full-scale range.

This paper presents a 16-bit, 18-MSPS flash-assisted SAR ADC with the HYSAS control logic fabricated in 40-nm CMOS. The HYSAS control logic combines the advantages of the synchronous and asynchronous logic, which can provide longer CDAC settling time and a more rational time allocation scheme than the synchronous and asynchronous control logic. The ADC achieves 76-dB SNDR and 94-dB SFDR under 18 MSPS for a 2.88 MHz sinusoid input signal, with 10-mW power consumption under 1.8/1.2 V power supply voltages.