In response to the existing challenges of difficult detection and potential leakage in wafer level vacuum packaging, a Pirani gauge design and processing method that is compatible with silicon micro-device processes and can be processed in parallel within the same cavity is proposed for vacuum degree detection after wafer-level vacuum packaging. The Pirani gauge structure is processed using SOI silicon wafers, and the device is packaged at the wafer level through gold-silicon bonding. At the same time, the longitudinal electrode lead-out method of Through Silicon-Vias(TSV) is adopted to improve the gas sealing issue. Test results show that the temperature coefficient of the Pirani gauge resistance in the linear range is 1.58 Ω/℃ , the detection sensitivity range is about 1~100 Pa, and the sensitivity reaches 61.67 Ω/ln(Pa). The proposed Pirani gauge can be processed in parallel with silicon micro-devices, providing a simple and feasible solution for in-wafer testing of the vacuum degree in wafer-level vacuum packaging cavities.