Optical Instruments, Volume. 46, Issue 5, 31(2024)
Design of ATE data storage and transmission system for optical chip testing
[8] [8] WANG X D, SHEN L Y, JIA M. The design optimization of DDR3 controller based on FPGA[C]Proceedings of the 2017 International Conference on Communications, Signal Processing, Systems. Singape: Springer, 2019: 17441750.
[14] [14] VERMA S, DABARE A S. Understing clock domain crossing issues[EBOL]. [2007−12−24]. https:www.designreuse.comarticles17372clockdomaincrossing.html.
Get Citation
Copy Citation Text
Qifan JIA, Xuanhong JIN, Pengcheng XIAO, Hangyu HE. Design of ATE data storage and transmission system for optical chip testing[J]. Optical Instruments, 2024, 46(5): 31
Category:
Received: Oct. 26, 2023
Accepted: --
Published Online: Jan. 3, 2025
The Author Email: JIN Xuanhong (judithking@vip.sina.com)