Optical Instruments, Volume. 46, Issue 5, 31(2024)

Design of ATE data storage and transmission system for optical chip testing

Qifan JIA1... Xuanhong JIN1,*, Pengcheng XIAO2 and Hangyu HE1 |Show fewer author(s)
Author Affiliations
  • 1School of Optical-EleCtrical and Computer Engineering, University of Shanghai for Science and Technology, Shanghai 200093
  • 2. School of Microelectronics Fudan University, Shanghai 201203, China
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    References(4)

    [8] [8] WANG X D, SHEN L Y, JIA M. The design optimization of DDR3 controller based on FPGA[C]Proceedings of the 2017 International Conference on Communications, Signal Processing, Systems. Singape: Springer, 2019: 17441750.

    [14] [14] VERMA S, DABARE A S. Understing clock domain crossing issues[EBOL]. [2007−12−24]. https:www.designreuse.comarticles17372clockdomaincrossing.html.

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    Qifan JIA, Xuanhong JIN, Pengcheng XIAO, Hangyu HE. Design of ATE data storage and transmission system for optical chip testing[J]. Optical Instruments, 2024, 46(5): 31

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    Paper Information

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    Received: Oct. 26, 2023

    Accepted: --

    Published Online: Jan. 3, 2025

    The Author Email: JIN Xuanhong (judithking@vip.sina.com)

    DOI:10.3969/j.issn.1005-5630.202310260120

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