Resistive random access memory (RRAM) has shown its great advantages as an emerging memory medium due to its 4F² high integration density, sub-pJ energy consumption, and good compatibility with CMOS technology^[1−3]. Owing to its non-volatile and parallel features, RRAM arrays are also widely exploited as the engine of in-memory analog computing^[4−7]. For both memory and analog computing applications, reducing the process variation has become a significant challenge^[6].

With the continuous shrinking of the physical geometry in every new generation of process technology, the lithographic variation, e.g., optical proximity effect, becomes increasingly severe^[7−11]. The lithographic variation introduces deviation between the mask pattern and the printed pattern^[12], affecting the device characteristics such as threshold voltage^{[13, 14]} and circuit performance in CMOS technology^{[15, 16]}.

An RRAM device is physically placed at the cross-junction of two adjacent metal layers (e.g., lower metal layer, M_x and upper metal layer, M_{x + 1}). It is usually fabricated together with the via or contact layer. The fabrication control of via/contact only requires the proper electrical connection between interconnect layers; however, the RRAM devices pose a higher requirement in controlling the lithographic variation as their electrical characteristic is highly dependent on the actual printing of the RRAM device, i.e. the area of printed pattern^[17−19]. Despite the use of optimized optical proximity correction (OPC) technique to improve its printability, the effect of lithographic variation can easily affect the printing of the RRAM devices, introducing severe circuit variations.

Presently, the researches on RRAM's variation primarily focus on random variations such as cycle-to-cycle uncertainty^[20] and random telegraph noise^[21]. Despite material engineering such as conductive filament confinement^[22] can alleviate the random variation, it is unable to solve the systematic process variation from lithography. To the best of our knowledge, there is yet a literature report on RRAM variation with the lithographic variation.

This work establishes an optical physical verification methodology for the RRAM array. The proposed methodology allows us to investigate how the lithographic variation affects the electrical characteristic of RRAM devices. Based on the geographical locations and lithography environments in the RRAM array, three clusters of RRAM devices are observed, and the dependence of conducting and switching variation on RRAM device length, RRAM device spacing, and array's size is investigated. In addition, the effectiveness of the optical proximity correction technique is investigated. This study aims to provide a good understanding of the important electrical characteristics of RRAM devices affected by lithographic variation and provides us with useful insights on the physical design of RRAM array to minimize the electrical variation of RRAM devices.

The remainder of this paper is as follows: Section 2 presents the lithography model, RRAM device model, and overall simulation flow. Section 3 presents the simulation results and the discussions. Section 4 concludes our work.

A model-based lithography simulation on the interconnect layers can be broken down into two steps (optical simulation and resist simulation)^[12]. The optical simulation calculates the distribution of light intensity, i.e., aerial image, through the calibrated optical model onto the mask pattern. The aerial image is then used as an input for resist simulation through a resist model, predicting the contour of the printed patterns^{[23, 24]}. In this work, the contact/via layer is adopted to model the RRAM array. Our simulation is based on a commercial proprietary Mentor Calibre lithography vector model. An annular illumination with an exposure wavelength of 193 nm is assumed. The numerical aperture of the projection optics is set to be 0.93. A VT5 model^[24] is used to model the resist. To evaluate the lithographic variation under different process conditions, simulations under different doses and focuses are performed. In the lithography process, the dose is defined as the amount of energy delivered by the light source compared to the nominal value, and the focus is defined as the focal adjustment relative to the nominal focus setting (represented by 0 nm). In this work, the dose is chosen to be 0.95, 1.00, and 1.05, respectively. The focus is chosen to be −100, −50, 0, 50, and 100 nm, respectively.

In this paper, the RRAM device model is based on Ref. [25]. The RRAM device is composed of an oxide layer sandwiched between the top electrode (TE) and the bottom electrode (BE), and the conductive and switching behaviors are attributed to the growth and rupture of the conductive filament (CF). The gap distance between the CF and TE is chosen as the state variable to control the internal state. In the SET process, a forward voltage is applied to drive the oxygen ions into the TE interface, thus leaving the oxygen vacancies and forming the CF. Thus, the gap distance and resistance value are reduced, as shown in Fig. 1(a). In the RESET process, the reverse voltage is applied to drive the oxygen ions to recombine with the CF, thus increasing the gap distance and resistance value, as shown in Fig. 1(b).

Given the gap distance, g, the current−voltage (I−V) relationship of the RRAM device is expressed as:^[25]

1I=I0exp(−gg0)sinh(VV0),

where I₀, g₀, and V₀ are the fitting parameters, and V is the applied voltage across TE and BE. However, the model does not explicitly consider the effect of the device area, which has an obvious effect on RRAM characteristics^[17−19]. Experimental studies have shown that for Cu_xSi_yO RRAM devices, the resistance has a negative linear dependency on the device area in the sub-90 nm region^[17]. This is mainly because the device area is almost equivalent to the dimension of the CF. For ZrO_x/HfO_x RRAM devices, this negative relationship can be observed from ~10² to ~10⁴ nm range^[26]. As the lithography variation does not depend on the type of RRAM device, we use a commonly-used model that is the same as Refs. [27−29] to describe the relationship between area and resistance. Hence, Eq. (1) is calibrated as follows:

2I=SS0I0exp(−gg0)sinh(VV0),

where S is the area of the printed RRAM pattern and S₀ is a constant. In addition, the gap evolution model in Ref. [25] is adopted to model the SET and RESET processes.

Fig. 2 illustrates the lithography physical verification methodology for RRAM devices proposed in this work. As illustrated in Fig. 3, the parameters including the number of rows, the number of columns, RRAM device length, and RRAM device spacing determine the layout of the RRAM array. These layouts are evaluated under the lithography simulation to determine the actual printed pattern of each individual RRAM device and to understand the electrical characteristics and variability of the RRAM devices. It is worth noting that the device model of each individual RRAM device is modified according to the actual printed area, allowing us to perform circuit simulation more accurately.

To evaluate the electrical characteristics of each individual RRAM device, a voltage signal is applied, as shown in Fig. 4(a). The voltage across TE and BE is composed of a positive voltage pulse (i.e., SET operation) followed by a negative voltage pulse (i.e., RESET operation). In addition, we define the resistance under an applied voltage of 0.1 V as the read resistance R_read. The use of a small applied voltage avoids causing destructive read operation and non-linear I−V distortion in analog computing applications^[30]. As shown in Fig. 4(b), R_read is changed to minimum read resistance R_on after SET operation and to maximum read resistance R_off after RESET operation. Fig. 4(c) shows an example of a simulated I−V curve. The simulation is based on the RRAM device (i.e., model Eq. (2)) under SET and RESET pulses as shown in Fig. 4(a). The simulated current is collected and its relationship with applied voltage is plotted. From Figs. 4(b) and 4(c), we extract the following parameters, which are important in the RRAM circuit design^[31]:

R_on: The minimum read resistance after SET.

R_off: The maximum read resistance after RESET.

V_set: The applied voltage on the RRAM device when the read resistance starts to decrease.

V_rst: The applied voltage on the RRAM device when the read resistance starts to increase.

Among them, R_on and R_off determine the memory window margin whereas V_set and V_rst determine the program voltage requirement. The variation of these parameters among the RRAM devices in an array affects the performances and variability of the circuit^[31−33].

We implement the lithography physical verification flow in Python language. The RRAM layout generation is based on the KLayout tool^[34]. The model-based lithography simulation is based on Mentor Calibre tool^[35], and the circuit simulation is performed by HSPICE tool^[36]. All the experiments are performed on a Linux server with 64 CPU cores.

Fig. 5(a) illustrates an example of a mask pattern and its actual printed size for a 32 × 32 RRAM array. The mask pattern of the RRAM device has a square shape design with 110 nm length. The RRAM device spacing is assumed to be 100 nm. As shown in Fig. 5(b), although all the RRAM devices have an identical mask pattern, the lithography process has caused the actual printed patterns to have a varying dimension, depending on their locations. For simplicity, we define the RRAM devices located at four corners of the entire array as corner devices and the other devices at the outermost layer as edge devices. The remaining RRAM devices are defined as the center devices. The center devices have more uniform lithography environments than edge devices and corner devices, i.e., these devices are surrounded by adjacent RRAM devices in all directions. Hence, the printed pattern has a symmetric circle as the mask pattern, which is consistent with the measurement results reported in Ref. [37]. The closer the RRAM is to the center, the more symmetrical the printed pattern. In contrast, for edge devices and corner devices, there are only three or two sides that are surrounded by other RRAM devices, leading to an asymmetric lithography environment in the four directions. Due to the optical proximity effect, these edge and corner devices tend to be closer to neighboring RRAM devices, resulting in pattern distortion and smaller printed areas. For example, the RRAM device at the location (420 nm, 420 nm) is closer to the center with an area of 6624 nm². The areas of RRAM devices at the location (210 nm, 0 nm) and (0 nm, 0 nm) are 5785 and 5128 nm², respectively. For a better illustration, we have shifted the location of the RRAM device from (420 nm, 420 nm) to (210 nm, 0 nm) and (0 nm, 0 nm), as shown in red. The deviation between the center device and the edge/corner device can be clearly observed.

Fig. 6 shows the simulation results of the device area using the same RRAM array as Fig. 5 under different process conditions. We observe that the device area of the printed RRAM patterns depends on the doses and focuses. The relative error of the average device area among different process conditions achieves up to 105%. Meanwhile, the device area has a similar distribution under different doses and focuses. To analyze the lithographic variation among different locations of RRAM cells, we identify two process conditions with the largest (dose = 1.05, focus = 0 nm) and smallest (dose = 0.95, focus = −100 nm) average device area as two process corners, which are denoted as maximum (max.) corner and minimum (min.) corner. In addition, the process condition with dose = 1.00 and focus = 100 nm is recorded as the typical corner.

The statistics of RRAM characteristics in the 32 × 32 RRAM array are shown in Fig. 7−Fig. 11. Fig. 7 shows the distributions of the printed RRAM patterns' area under different process conditions. We observe the RRAM devices can be categorized into three clusters, which are corresponding to the center devices (87.9% of the total RRAM devices), edge devices (11.7%), and corner devices (0.4%), respectively. The device area values of corner devices are smaller than edge devices, whereas the center devices have the largest device area values. Fig. 8 and Fig. 9 show the R_on and R_off distributions, respectively. Similar observation with device area distribution can be found in R_on and R_off distributions, where R_on and R_off can also be categorized into three clusters, i.e., center devices, edge devices, and corner devices. We quantitatively evaluate the lithography-induced variation using the relative error between the largest and the smallest values as follows:

3variation=|xmax|−|xmin||xmin|,

where x represents R_on, R_off, V_rst, and V_set. In the typical corner, the variation of R_on and R_off due to different lithography environments of different RRAM devices is up to 27%−29%. The variation among different RRAM devices is significantly affected by dose and focus. For example, the R_on and R_off variation among different RRAM devices increases to 289% for the min. process corner. Fig. 10 and Fig. 11 show the distribution of V_rst and V_set of center, edge, and corner devices, respectively. The corner devices have higher reset voltage values than center devices, leading to 2%−9% V_rst variation. The variation of V_rst is mainly because of the variation of device area. As the corner devices have smaller device areas, their V_rst values are higher than the center devices, which is consistent with the experimental observations^[17]. In contrast, the variation of V_set is significantly lower (not higher than 2%), which is because the V_set has little dependency on the device area^[17].

Figs. 12(a)−12(c) show the relationship between R_on distribution and the RRAM device length. The RRAM device length ranges from 106 to 120 nm. The results indicate that R_on becomes smaller as the RRAM device length increases. For example, in the typical corner, the average R_on in the RRAM array is reduced by 2.1× when the RRAM device length increases from 106 to 120 nm. In addition, the variation of R_on among RRAM devices at different locations is also significantly reduced as the RRAM device length increases. A larger RRAM device length reduces the variation. For example, in the typical case, the variation is reduced from 45% with a RRAM device length of 106 nm to 14% with an RRAM device length of 120 nm. Meanwhile, the process condition also has a significant impact on the variation. For the min. corner, some RRAM cells cannot be printed when the RRAM device length is smaller than 109 nm. R_off shows the same trend as R_on, where the resistance is reduced by 2.1× and the variation among different locations is reduced from 46% to 15%.

The V_rst and V_set with different RRAM device lengths are compared in Figs. 12(g)−12(i). With the increase of RRAM device length from 106 to 120 nm, the average V_rst is reduced by 8%, and the variation of V_rst is reduced from 4% to 2% in the typical corner. The average V_set is only reduced by 1%, indicating little dependency on the RRAM device length. Furthermore, the variation of V_set among different locations is not higher than 2%. This is similar to the observation reported in Ref. [17] that the V_set and V_rst are less sensitive to the device area than R_on and R_off.

Figs. 13(a)−13(c) and Figs. 13(d)−13(f) report the changes in R_on and R_off values due to different device spacings, respectively. As the RRAM device spacing increases, the optical proximity effect gradually weakens, yielding a smaller device area. Hence, the R_on and R_off increase. For example, in the typical corner, when the RRAM device spacing increases from 70 to 160 nm, the average values of R_on and R_off increase by 1.4× approximately. Meanwhile, we observe that in the typical and max. corners, a larger RRAM device spacing reduces the variation among the RRAM devices, where it comes at the cost of the additional area. However, in the min. corner, the isolated lithography environment results in a too smaller device area of the corner devices. Hence, the variation among RRAM devices may become larger with the increase in the device spacing.

Figs. 13(g)−13(i) compare the V_rst and V_set with different RRAM device spacings. In the typical corner, when the RRAM device spacing increases from 70 nm to 160 nm, the V_rst has increased by 4% while its variation has reduced from 3% to 0.7%. In addition, the V_set has a minimum dependency on RRAM device spacing, and its variation is less than 2%.

The effects of RRAM array's size on R_on and R_off are shown in Figs. 14(a)−14(c) and Figs. 14(d)−14(f). As the increase in the number of rows and number of columns of the RRAM array, the average values for R_on and R_off decrease. In the typical corner, R_on and R_off decrease by 11% and 12% from 4 × 4 to 64 × 64 array. This is primarily because the center devices occupy a larger proportion in a larger size of the RRAM array. However, the variations of R_on and R_off are 26%−30% for RRAM array sizes ranging from 4 × 4 to 64 × 64. Note that the variation is determined by the RRAM devices with the largest and smallest R_on/R_off, which correspond to corner devices and center devices, respectively. As the lithography environments of corner devices and the center devices are independent with RRAM array size, the variation has minimum dependence on the array size. In addition, the V_rst and V_set are evaluated and compared in Figs. 14(g)−14(i). The variation of V_set is smaller than 3% for all the evaluated array sizes and process conditions. For V_rst, in the typical corner, the variation changes < 1% from 4 × 4 to 64 × 64 array size.

To compensate for the image error, the optical proximity correction (OPC) technique is widely used in the modern semiconductor manufacturing flow^[38]. By changing the patterns on the lithography mask, OPC tries to reproduce the original layout drawn by the designer on the semiconductor wafer as well as possible. We apply the OPC technique to the original layout to investigate its effectiveness on the RRAM array layout using Mentor Calibre tool^[39]. The OPC is applied based on the contact/via optical and lithography models. The relationship between average device area and device spacing with and without the OPC technique applied is shown in Fig. 15(a), and the variation result is shown in Fig. 15(b). We have simulated device areas and their variations under different process conditions. The blue color shows the maximum and minimum device areas and variations without applying the OPC technique, whereas the red color shows the results with applying the OPC technique. From Fig. 15(b), we observe that the application of the OPC technique significantly reduces the variation among different RRAM devices. For example, when the device spacing equals 140 nm, the variation is reduced from 12%−77% to 1%−9%. Table 1 compares the lithography variation of different RRAM parameters before and after applying the OPC technique (device length and spacing are 115 and 140 nm, respectively). In the typical corner, the OPC technique reduces the variation of R_on and R_off from 13.9% and 13.7% to 1.7% and 1.1%, respectively. For the minimum corner, the effect of the OPC technique is more obvious, which reduces the variation of R_on and R_off from 76.5% to 8.4% and 8.1%, respectively. For V_set and V_rst, the OPC technique reduces the variation by 0.65% in average.

Fig. 16(a) shows the physical layout before and after the OPC technique was applied. Applying the OPC technique increases the geometric size of the RRAM pattern on the layout. Hence, the area of the printed RRAM pattern also increases, resulting in a decrease in R_on and R_off, as shown in Fig. 17. For example, when the device spacing is 140 nm in the typical corner, the average R_on is reduced by 4.2×. However, the decrease in R_on and R_off results in higher power consumption^[40]. In addition, due to the increase in the RRAM's geometric size, different RRAM devices may cause a short circuit when device spacing is smaller than 140 nm, as shown in Fig. 16(b). We should note that this short circuit path will not be a severe issue for the contact/via layers (i.e., the use of multiple contacts/vias to reduce their voltage drop). This is because the purpose of contact/via layers is to ensure electrical connections between the different metal or polysilicon layers. However, the short circuit path will result in the functional failure for both RRAM-based memory circuits or the in-memory computing circuits. Hence, sufficient device spacing needs to be ensured before applying the conventional OPC technique, resulting in a larger area of the entire RRAM array circuit. Note that achieving the most optimal performance can be achieved by developing specific OPC receipts for different sizes of RRAM arrays; however, lithographic variations cannot be overcome by doing so.

In summary, this paper has investigated the impact of lithographic variation on the electrical characteristics of RRAM devices. We have developed an optical physical verification methodology on different RRAM device lengths and RRAM device spacings. The important electrical characteristics for circuit design including R_on, R_off, V_set, and V_rst are evaluated. The results reveal that the RRAM devices can be categorized into three clusters according to their locations and lithography environments. Compared to V_set and V_rst, R_on and R_off are more sensitive to the layout. The variation of R_on and R_off can be effectively reduced either by increasing the RRAM device length or applying the OPC technique, whereas it results in a higher power and area consumption. Therefore, it is important to design and optimize the layout of the RRAM array automatically according to different circuit and application specifications.