A column-level ADC-based readout circuit design is introduced in this paper. The size of the readout circuit is 640×512, the pitch is 15μm. The column level digital ADC structure adopts a three-order incremental Sigma Delta ADC structure, and its quantization resolution is 16 bits. The maximum frame frequency of the readout circuit is 240 Hz, and the maximum power consumption is 250 mW, and the output method is LVDS mode.