Single Event Upset(SEU) effects are a common cause of processor failures in aerospace environments, necessitating effective protective designs to enhance the reliability of high-altitude equipment in the fields of aviation and astronautics. Traditional embedded reliability protection designs typically employ either single hardware or software approaches: implementing Triple Modular Redundancy(TMR) through software requires substantial CPU resources; employing hardware circuits does not facilitate error reporting. This paper focuses on the PPC460 processor as the target system, discussing an advanced reliability enhancement design method utilizing Field-Programmable Gate Array(FPGA) technology for the PPC460 processor. The approach integrates an extended Hamming code encoding and decoding algorithm, parity checking, and Triple Modular Redundancy techniques. By synergistically combining software and hardware strategies, it improves the correctness of data within the storage space, reduces CPU resource consumption, and effectively realizes high-security, high-reliability, and interference-resistant protection for critical data on the PPC460 processor in special complex environments.